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Carbon Nanotube Field Effect Transistor

electrical characteristics of CNTFET

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Carbon Nanotube Field Effect Transistor

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  1. Course: Nanoelectronic Device Arpan Deyasi Nanoelectronic Carbon Nanotube Field Effect Transistor Device Arpan Deyasi RCCIIT, India 07-06-2021 Arpan Deyasi, RCCIIT, India 1

  2. Setback of MOSFET Continuous downscaling of MOSFET leads to …………………… Arpan Deyasi ➢ Short-channel effect Nanoelectronic ➢ Higher leakage current Device ➢ Closeness of ON and OFF level in digital circuit due to reduction of saturation current at higher rate compared with reduction rate of threshold voltage ➢ Excessive variation of process technology 07-06-2021 Arpan Deyasi, RCCIIT, India 2

  3. Solutions to Overcome ➢ High-K dielectric, highly conductive gate electrode, different substrate material replacing Si Arpan Deyasi ➢ Novel geometries Nanoelectronic ➢ New architectures Device 07-06-2021 Arpan Deyasi, RCCIIT, India 3

  4. Why MOSFET can be replaced via CNTFET? Arpan Deyasi 1-D ballistic transport of electrons and holes Nanoelectronic High drive current and large transconductance Device High temperature resilience and strong covalent bond 07-06-2021 Arpan Deyasi, RCCIIT, India 4

  5. Comparison with MOSFET Switching takes place in MOSFET by altering channel resistivity, but for CNTFET, it occurs through modulation of channel resistance Arpan Deyasi Higher drive currents of CNTFET compared with MOSFET Nanoelectronic Higher transconductance Device Higher carrier mobility Higher gate capacitance leads to improved carrier transport, which provides better ON-current performance 07-06-2021 Arpan Deyasi, RCCIIT, India 5

  6. Classification of CNTFET Arpan Deyasi CNTFET Nanoelectronic Based on geometry Device Based on operation MOSFET Coaxial Gate Bottom Gate Top Gate Schottky barrier 07-06-2021 Arpan Deyasi, RCCIIT, India 6

  7. Bottom-gate CNTFET Arpan Deyasi CNT Nanoelectronic Source Drain Device Silicon Oxide Substrate Metal contact for back side 07-06-2021 Arpan Deyasi, RCCIIT, India 7

  8. Bottom-gate CNTFET Preliminary CNTFET Arpan Deyasi ❑ high on-state resistance Nanoelectronic ❑ low transconductance Device ❑ no current saturation ❑ required high gate voltages to turn ON 07-06-2021 Arpan Deyasi, RCCIIT, India 8

  9. Top gate CNTFET Arpan Deyasi Gate Dielectric Source Nanoelectronic Top Gate Drain CNT Device Insulator Substrate Doped Silicon 07-06-2021 Arpan Deyasi, RCCIIT, India 9

  10. Top gate CNTFET Improved architecture than bottom-gate CNTFET Arpan Deyasi ❑ better subthreshold slope Nanoelectronic ❑ Higher transconductance Device ❑ negligible hysteresisin terms of threshold voltage shift 07-06-2021 Arpan Deyasi, RCCIIT, India 10

  11. Coaxial gate CNTFET Arpan Deyasi Nanoelectronic Device Gate Source Drain Better electrostatic control over channel 07-06-2021 Arpan Deyasi, RCCIIT, India 11

  12. Schottky Barrier CNTFET Arpan Deyasi Nanoelectronic Gate Dielectric Device Drain Source CNT Dielectric Gate 07-06-2021 Arpan Deyasi, RCCIIT, India 12

  13. Schottky Barrier CNTFET SB-CNFET works on the principle of direct tunneling through the Schottky barrier at the source channel junction Arpan Deyasi The barrier width is controlled by the gate voltage and hence the transconductance of the device depends on the gate voltage Nanoelectronic Device At low gate bias, large barrier limits the current in the channel . As gate bias is increased, it reduces the barrier width, which increases quantum mechanical tunneling through the barrier , and therefore increases current flow in transistor channel In SBCNFET, the transistor action occurs by modulating the transmission coefficient of the device 07-06-2021 Arpan Deyasi, RCCIIT, India 13

  14. MOSFET like CNTFET overcome problems in SB-CNFET by operating like normal MOSFET Arpan Deyasi operates on the principle of modulation the barrier height by gate voltage application Nanoelectronic Drain current is controlled by number of charge that is induced in the channel by gate terminal Device 07-06-2021 Arpan Deyasi, RCCIIT, India 14

  15. I-V characteristic Arpan Deyasi  =  +  ΦGS: work function difference between gate and substrate Nanoelectronic GS GC CS ΦGC: work function difference between gate and carbon nanotube channel Device ΦCS: work function difference between carbon nanotube channel and substrate 07-06-2021 Arpan Deyasi, RCCIIT, India 15

  16. I-V characteristic Potential balance equation Arpan Deyasi Q C Nanoelectronic =  − + V V cnt , GB cnt s fb 1 ox VGB: gate-to-body bias Device Ψcnt,s: potential at interface of gate oxide and carbon nanotube channel Qcnt: total charge in carbon nanotube Vfb: flatband voltage Cox1: oxide capacitance at front-gate 07-06-2021 Arpan Deyasi, RCCIIT, India 16

  17. I-V characteristic Arpan Deyasi  2 l ox = C 1 Nanoelectronic ox         1 + + + 2 2 t r t r t r ox ox ox ln 1 1 1 Device tox1: gate oxide thickness at front surface l: channel length r: channel radius 07-06-2021 Arpan Deyasi, RCCIIT, India 17

  18. I-V characteristic Using carrier concentration modeling and charge modeling equations Arpan Deyasi V Nanoelectronic =  +  (  + , ) f V V , , GB cnt s cnt s CB fb VCB: channel to back-gate bias Device 07-06-2021 Arpan Deyasi, RCCIIT, India 18

  19. I-V characteristic          − + (  − −        ) E E q V Arpan Deyasi , 0 F C cnt s cb exp I k T B cb Nanoelectronic for ψcnt,s<(VCB+φ0) (  = , ) f V ( ) , cnt s 2 Device  +  − −  − 2 E q qV q E , 0 F cnt s cb C k T B for ψcnt,s>=(VCB+φ0) qlN C  = C ox 1 07-06-2021 Arpan Deyasi, RCCIIT, India 19

  20. I-V characteristic Arpan Deyasi                        − + (  − −        (0) E E q V Nanoelectronic ln 1 exp +     −    , 0 F C cnt s SB k T qk T  B = I B h ln 1 exp + Device DS      − + (  − −     ( ) l E E q V , 0 F C cnt s DB k T B 07-06-2021 Arpan Deyasi, RCCIIT, India 20

  21. Comparison of n-FET and p-FET Arpan Deyasi Palladium (Pd) is the best contact metal found for p-FETS (no Schottky Barrier at the interface) Nanoelectronic Aluminium is used to create near Ohmic contacts with the SNT in n-FET Device Small SBs exist at the interface between Al and CNT Overall performance of p-FET is better than n-FETS 07-06-2021 Arpan Deyasi, RCCIIT, India 21

  22. Advantage of CNTFET Better control over channel formation Arpan Deyasi Lower threshold voltage Nanoelectronic Lower subthreshold slope Device Higher electron mobility Higher current density Higher transconductance 07-06-2021 Arpan Deyasi, RCCIIT, India 22

  23. Applications of CNTFET Interconnect with very low loss: Logic circuits: multiple level interconnects with negligible parasitic effects Arpan Deyasi Nanoelectronic Memory design Device Biosensor RF circuits Energy source in battery and solar cell 07-06-2021 Arpan Deyasi, RCCIIT, India 23

  24. Drawbacks of CNTFET Arpan Deyasi Defect and failure rate at device and circuit level is higher than traditional CMOS based circuits Nanoelectronic Degrades when exposed to Oxygen, which decreases its lifetime Higher production cost owing to difficulties in mass production Device 07-06-2021 Arpan Deyasi, RCCIIT, India 24

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