Local Trigger Control Unit prototype

1. Local Trigger Control Unitprototype M. Della Pietra, A. Di Cicco, P. Di Meo, G. Fiorillo, P. Parascandolo

2. LTCU Prototype overview • 1 board for each of 20 Racks per chamber (80 in total) where the induction II and collection planes are cabled in • It receives as input 9 + 9 analogical32coming from the v791 boards (generally 9 of 2nd induction and 9 of collection) CH_out 9 T1 32 from v791 LTCU TCU T2 9 • LTCU discriminates the 18 inputs comparing them with a remote controlled threshold (one for each input). It can mask the noisy inputs • It gives as output two Trigger proposals (T0 and T1), each one coming from FastOR of 9 inputs. • It measures the rate of Trigger proposals for each input. • All the board functionalities are driven by a remote controller through RS232

3. BACK FRONT LTCU prototype layout diagram PC RS_232 v793 Oscillator 10 MHz Ch_out Channel Out Xilinx Spartan 2 Induction II plane signal T1n Collection plane signal TCU T2n 18 discriminators 9 9  (from collection plane) Pulse Test 9 Pulse Test No Input v791 DAC 9 VTh  (from induction II plane) VTh

4. - + + - LTCU – Input for 1ch Test pulse input signal from FPGA TL712 - Discriminator 60 KHz Noise filter RC filter - Dn to FPGA Sn from v791 + SDATA from FPGA DAC SCLKfrom FPGA LM6171 – LM6172 Voltage follower to drive discriminator input Vref = ~ 250 mV 8 bit = 256 step  0.1 mV step TLC5628C 8bit – 8ch serial

5. Power supply input 10 MHz Oscillator No input LM6172 to drive threshold discriminators input XILINX Spartan 2 XC2S100 – 5PQ208 LM6171 - Input voltage followers TLC5628C 8bit – 8ch serial 18 TL711 discriminators 18 ASum input 2 FastOR out RS232 in\out 18x1 Mux out VME controller in\out LTCU prototype Back Front

6. LTCU – FPGA block diagram D[17-0] Chout 18 MUX D[8-0] T1 INPUT Interface Mask & fast OR 9 T2 Read channel 9 Internal Xilinx Spartan 2 RAM Fired channels recorder D[17-9] Sync 18 18 D[17-0] Read mask Write mask RS_232 interface S_IN Time window S_OUT Read cnt SDATA Write DAC 3 DAC interface 4 Test pulse 3 SCLK

7. Status of FPGA logic design • RS232 interface logic are implemented and simulated • Test pulse and DAC logics are under test on board • Input interface and FastOR are implemented • Mask block and fired channel recorder must be designed

8. FastOR block RS232 – interface block LTCU – FPGA contents: schematic

9. LTCU - RS232 interface • Receives RS232 serial data: • Write mask: 4 byte (1 Control Word + 3 byte data); • Read mask: 1 byte (CW); • Write DAC: 3 byte (1 CW + 2 byte data); • Read cnt: 2 byte (1 CW + 1 byte data); • Time window: 1 byte (CW); • Test pulse: 1 byte (CW); • Read channel: 2 byte (1 CW + 1 byte data). • Gives in output: • External signal: RS232 serial out, 3 signals for each DAC, 4 test pulse signals; • Internal signal: write mask words, read channel word, read count word, time window signal

10. 10 bit SIPO input register and RS232 controller Control word decoder DAC controller Read Cnt, Mask, Time window and Read channel controller Operation controller LTCU - RS232 interface: schematic

11. RS232 datasheet • Asyncronous one directional two data lines bus • Every transfer is composed by start bit, 8 bit data (from LSB to MSB), stop bit. • Rate: 9600 bps (100ms pulse duration) • Lines standby state: H

12. LTCU - RS232 controller • Recognizes start transition. • Gives ten sampling pulses: • First pulse after 50ms from falling edge of the start transition • Then every 100ms • Gives load pulse after stop bit. • Data are stored in an external SIPO 10 bit register each sampling pulse

13. Start detector and sync block Load and reset generator Sampling pulses generator LTCU - RS232 controller: schematic

14. LTCU – RS232 controller: simulation Data are correctly stored • Simulation input conditions: • 1 byte data: 01010101 (55\HEX) • data rate: 9600 bps • Input data pulse duration: 100 ms • First sampling pulse 50 ns after Start bit H-L transition • Sampling pulse period after first: 100 ms

15. LTCU – FPGA operation • WRITE_MK: mask input channel. Control word byte: 00100000 • READ_MK: read which channels are masked. CW byte: 01100000 • WRITE_DAC: set discriminators threshold. CW byte: 00010000 • READ_CNT: read channel hits from memory. CW byte: 01010000 • TEST_P: test pulse mode. CW byte: 000010tt (2 LS bits to select channels to test) • T_WIN: set time window to count fired input. CW byte: 000001ww (2 LS bits to select time window width) • READ_CH: set one input channel to output. CW byte: 11000000

16. LTCU – Control word decoder • Receives 1 byte data • Decodes the control word received • Give a different signal for each control word

17. LTCU – Control word decoder: schematic

18. LTCU – Operation controller • FSM designed in ONE HOT logic; • Receives signal from Control word controller; • Gives different enable signal for each controller of RS232 interface; • Give test pulse and time window signals.

19. 2 LS bit decoder 2 LS bit decoder Read mask: 1 states Test pulse: 1 states Time window: 1 states Write mask: 4 states Write DAC: 3 states Read cnt: 2 states Time windows width Read channel: 2 states LTCU – Operation controller: schematic

20. LTCU – Operation controller: simulation EX: Write DAC • First LOAD pulse enables Control word controller • Control word controller decodes Write DAC command and gives a pulse on WRITE_DAC line • After WRITE_DAC pulse the FSM gives 2 pulse to store 2 byte data Data are correctly stored

21. DAC datasheet (I) • TLC5628 – octal 8bit DAC; • Serial interface digital data input; • Digital data are clocked into internal DAC serial register on the falling edge of the clock signal; • DAC output are updated only when LOAD becomes low (L); • 12 bit data transmission: 3bit DAC channel + 1bit range RNG (fixed to L) + 8bit voltage code;

22. Setup time data input tsu (DATA-CLK): min 50ns; Hold time data input tv (CLK-DATA): min 50ns; Setup time clock eleventh falling edge to load pulse tsu (CLK-LOAD): min 50ns; LOAD pulse duration tw: min 250 ns; Setup time load to new clock transmission tsu (CLK-LOAD): min 50ns; Clock frequency: max 1 MHz; DAC datasheet (II)

23. LTCU - DAC controller • Receives two byte data: • LS byte: CODE [7-0] • MS byte: XXX A1_DAC A0_DACA2_CH A1_CH A0_CH • Give serial clock, serial data and load to selected DAC on board

24. Outputs Serial Clock and shift pulse generator DAC address decoder Two PISO input registers Load and reset generator LTCU - DAC controller: schematic

25. LTCU - DAC controller: simulation Datasheet conditions respected • Simulation input conditions: • MS byte: 000 00001 (01\HEX): DAC0 – Channel B selected • LS byte: 01010101 (55\HEX) • Clock pulse duration: 1.6 ms • Load pulse duration: 300 ns • Last bit hold time (CLOCK-DATA): 400 ns • Setup time (CLOCK-LOAD): 100 ns • Setup time (DATA-CLOCK): 800 ns • Hold time (CLOCK-DATA): 800 ns

26. LTCU – FPGA preliminary occupancy Occupancy 11%

27. LTCU – Control Software • LTCU prototype is controlled via RS232 by LTCU Control software developed in NI Labview; • The LTCU Control drives all the boad functionalities; • Software is partially developed: ready up to now DAC threshold controller and Test pulse controller

28. LTCU – Slow Control software: DAC threshold controller The transmission start when send button is pressed Each channel threshold can be set Only enabled channels are sent to LTCU All channels can be set together

29. LTCU – Slow Control software: Test pulse controller Only enabled channels are tested when Send button is pushed

30. Conclusions • The LTCU prototype board are printed • The electric test of board is in progress • The LTCU RS232 interface and its all functionalities are designed and simulated • The LTCU control software is partially developed

31. To do • Design Fired channels recorder • Post-layout simulation of full FPGA logic • Test board functionality • Test with detector signals