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Draft Technology Table for High-Performance Logic

Draft Technology Table for High-Performance Logic. High-Performance Logic Scaling (IEDM Comparison). Benchmarks taken from IEDM publications; chose only technologies within 1-2 years of production. IEDM Papers with leading-edge bulk (non-SOI) performance selected (Moto, TI, Intel).

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Draft Technology Table for High-Performance Logic

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  1. Draft Technology Table for High-Performance Logic

  2. High-Performance Logic Scaling (IEDM Comparison) • Benchmarks taken from IEDM publications; chose only technologies within 1-2 years of production. • IEDM Papers with leading-edge bulk (non-SOI) performance selected (Moto, TI, Intel). • Apparent discontinuity at year 2001 is an artifact due difference between IEDM publication date and ITRS production node date. • 17% historical trend is consistent with past IEDM data as well as with the previously used 2000 ITRS projection for local-clock frequency.

  3. Scaling of Different Device Performance Factors • Channel-length scaling has the greatest impact on continued device performance. • Power supply voltage can not be scaled as aggressively as other device performance factors in order to maintain adequate overdrive (Vdd-VT). • New device technology improvements (SOI/low-temp/higher-mobility materials) will be needed to achieve required transconductance increase in later years (in addition to Tox scaling).

  4. Scaling of Different Device Hazard Factors • Gate-oxide effective E-field is increased by 50% by 2016. • Non-scalability of Tox/Lgate will increase short-channel effects. Project potential need for dual-gate SOI devices by the 2007 (65nm) node. • Voltage non-scalability will result in significantly increased lateral high-field effects (mitigation of these effects will be key device design challenge).

  5. Feedback to Other ITRS TWG Groups • Design TWG: • Front-end performance can continue to scale at historical rate. • Both dynamic & static power dissipation must be dealt with at the design and system level (not through Vdd scaling). • Circuit/system design must now account for significantly higher sub-threshold and gate leakage current (devices approach bipolar-like characteristics). • Front-End-Process TWG: • Projection of Tox electrical requirements has been made. • Specification made for maximum gate-tunneling/junction leakage. • Scaling scenario proposed for high-K gate dielectrics. • Rsd allowed to become larger percentage of channel resistance; however, still require 2X reduction in parasitic Rsd value by 2016. • Scaling scenario for gate electrode depletion has been proposed (impacts metal gate introduction point). • Impact of parasitic fringe/overlap capacitance on device performance has been evaluated (impacts gate stack aspect ratio and composition).

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