Breakpoint Module

1. Breakpoint Module

2. Break Module Features Hardware breakpoints are used to debug software on the HCS12 CPU by comparing actual address and data values to predetermined data in setup registers. A successful comparison will place the CPU in background debug mode (BDM) or initiate a software interrupt (SWI). The Breakpoint Module contains two modes of operation: • Full or Dual Breakpoint Mode – Compare on address and data (Full) – Compare on either of two addresses (Dual) • BDM or SWI Breakpoint – Enter BDM on breakpoint (BDM) – Execute SWI on breakpoint (SWI) • Tagged or Forced Breakpoint – Break just before a specific instruction will begin execution (TAG) – Break on the first instruction boundary after a match occurs (Force) • Single, Range, or Page address compares – Compare on address (Single) – Compare on address 256 byte (Range) – Compare on any 16K Page (Page) • Compare address on read or write on forced breakpoints • High and/or low byte data compares

3. Break Module Block Diagram BKPCT0 Break Point Control 0 BDM SWI Expansion Addresses [19:14] BKPCT1 Break Point Control 1 Compare Block Address [15:0] Write Data [15:0] Read Data [15:0] BKP0X Break Point 1 Expans. Compare Expansion Addresses BKP0H Break Point 1 High Byte Compare Address High BKP0L Break Point 1 Low Byte Compare Address Low BKP1X Break Point 2 Expans. Compare Expansion Addresses Address High BKP1H Break Point 2 High Byte Compare Data/Address High MUX Data High Address Low BKPC1L Break Point 2 Low Byte Compare Data/Address Low MUX Data Low Register Block Compare Read Data High Compare Read Data Low

4. HCS12 BDM & In-circuit emulation Background Debug™ Mode (BDM) Advantages: • Low-cost, real-time emulation capabilities • Use of all of the MCU functions: non-intrusive debugging through a single, dedicated pin • In circuit FLASH programming and debugging - NEVER DESOLDER AGAIN! • Single step or Run the application code on the target processor • Conditional Hardware Breakpoints • Eliminates the need for cumbersome emulator cables • View and change internal registers and memory in real-time. Disadvantages: • Some hardware implementations do not include emulation memory • Cannot see the address or data bus for very timing critical applications In-circuit Emulation (ICE) Advantages: • Bus state analysis without the need for a logic analyzer • Real-time tracing functionality for complex timing systems • Emulation Memory • Performance analysis Disadvantages: • More expensive system and development costs • Somewhat cumbersome emulation modules and connectors • Cannot easily look into the MCU after the product is in the field

5. Serial Debug Interface (SDI) Motorola’s Serial Debug InterfaceAn in-circuit debugger that makes use of Background Debug Mode (BDM). Allows quick verification of embedded software applications SDI when used with compatible debug software, allows users to view and modify their application on the fly. The SDI is connected between the computers serial port and a 10-pin BDM connector on the target system. BDM interface is a 10-pin connection between the MCU control signals and the user’s test control logic. Optimized for 8 MHz CPU clock!

6. SDI Features • Hardware and Software Components: • 6-pin interface connector for HC12 / HCS12 MCU devices • 10-pin interface connector for M68HC16 or M68300 MCU devices • SDBug software, which supports source-level debugging and on-board device and flash EEPROM programming. NOTE: SDBug is ordered separately • System Requirements: • 486-based or higher PC running DOS 5.0 or higher • RS-232C serial port for communications I/O • +5-volt power supply (when the low-voltage version is being used). • Selecting and Ordering the SDI:Choosing the correct SDI for a particular development project depends on: • the MCU device family upon which the target application is based • the SDI voltage version that is needed.NOTE: The SDI hardware and software are ordered separately

7. Breakpoint Registers (1 of 4) BKPCT0 - Breakpoint Control Register 0 BKEN - Breakpoint Enable. This bit enables breakpoint operation. 0 = Breakpoint module off. 1 = Breakpoint module on. BKFULL- Full Breakpoint Mode Enable This bit controls whether the breakpoint module is in Dual Mode or Full Mode 0 = Dual Address Mode enabled. 1 = Full Breakpoint Mode enabled. BKBDM - Breakpoint Background Debug Mode Enable This bit determines if the breakpoint causes the part to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI) 0 = Go to Software Interrupt on a compare. 1 = Go to BDM on a compare. BKTAG - Breakpoint on Tag This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint 0 = On match, break at the next instruction boundary (force). 1 = On match, break if the match is an instruction that will be executed (tagged).

8. Breakpoint Registers (2 OF 4) BRKCT1- Breakpoint Control Register 1 BK0RW— R/W Compare Value When BK0RWE=1, this bit determines the type of bus cycle to match on first address breakpoint. When BK0RWE=0, this bit has no effect. 0 = Write cycle will be matched. 1 = Read cycle will be matched BK1RWE — R/W Compare Enable In Dual Mode, this bit enables the comparison of the R/W signal to further specify what causes a match for the second address breakpoint. This bit is not useful on tagged breakpoints or in Full Mode and is therefore a don’t care. 0 = R/W is not used in comparisons. 1 = R/W is used in comparisons. BK1RW — R/W Compare Value When BK1RWE=1, this bit determines the type of bus cycle to match on the second address breakpoint.When BK1RWE=0, this bit has no effect. 0 = Write cycle will be matched. 1 = Read cycle will be matched. BK0MBH:BK0MBL - Breakpoint Mask High Byte and Low Byte for First Address. In Dual or Full Mode, these bits may be used to mask (disable) the comparison of the high and low bytes of the first address breakpoint. X:0 = Full Address Compare 0:1 = 256 Byte Address Range 1:1 = 16K Byte Address Range BK1MBH:BK1MBL - Breakpoint Mask High Byte and Low Byte for Second Address. In Dual or Full Mode, these bits may be used to mask (disable) the comparison of the high and low bytes of the second address breakpoint. X:0 = Full Address Compare 0:1 = 256 Byte Address Range 1:1 = 16K Byte Address Range BK0RWE — R/W Compare Enable Enables the comparison of the R/W signal for first address breakpoint. This bit is not useful in tagged breakpoints. 0 = R/W is not used in the comparisons. 1 = R/W is used in comparisons.

9. Breakpoint Registers (3 OF 4) BKP0X - First Address Memory Expansion Breakpoint Register BKP0X register contains the data to be matched against expansion address lines when Page is selected. BK0V[5:0] - First Address Breakpoint Expansion Address Value BKP0H - First Address High Byte Breakpoint Register BKP0H - This register is used to set the breakpoint when compared against the address high byte. BKP0L - First Address Low Byte Breakpoint Register BKP0L - This register is used to set the breakpoint when compared against the address low byte.

10. Breakpoint Registers (4 of 4) BKP1X - Second Address Memory Expansion Breakpoint Register BKP1X register contains the data to be matched against expansion address lines when Page is selected. BK1V[5:0] - First Address Breakpoint Expansion Address Value. BKP1H - Data (Second Address) High Byte Breakpoint Register BKP0H - This register is used to set the breakpoint when compared against the address high byte. In Full Mode, this register is used to compare against high order data lines. BKP1L - Data (Second Address) Low Byte Breakpoint Register BKP0L - This register is used to set the breakpoint when compared against the address low byte In Full Mode, this register is used to compare against high order data lines..