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An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts

An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts. Haihua Su, Sani R. Nassif IBM ARL. Sachin S. Sapatnekar ECE Department University of Minnesota. Outline. On-chip decap overview Modeling and noise analysis

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An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts

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  1. An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts Haihua Su, Sani R. Nassif IBM ARL Sachin S. Sapatnekar ECE Department University of Minnesota ISPD'02, San Diego, CA

  2. Outline • On-chip decap overview • Modeling and noise analysis • Problem formulation and Adjoint sensitivity analysis • Decap sizing and placement scheme • Experimental results • Conclusion ISPD'02, San Diego, CA

  3. On-chip Decoupling Capacitors • Non-switching gate capacitance • Thin oxide capacitance w: width of decap h: height of decap tox: thickness of thin oxide ox: permittivity of SiO2 ISPD'02, San Diego, CA

  4. Decoupling Capacitor Models • 1st order model • 2nd order model (non-idealities) ISPD'02, San Diego, CA

  5. + Power Network Modeling • Power Grid: resistive mesh • Cells: time-varying current sources • Decaps: 1st order or 2nd order decap model • Package: inductance + ideal constant voltage source ISPD'02, San Diego, CA

  6. z(j) + Waveform of node j on VDD grid Power Grid Noise Analysis • Noise metric: shaded area Vj Z= S z(j) Reference: A. R. Conn, R. A. Haring and C. Visweswariah, Noise Considerations in Circuit Optimization, ICCAD’98 ISPD'02, San Diego, CA

  7. Formulation - Constrained Nonlinear Programming Problem • MinimizeZ(wj), j = 1..Ndecap • Subject to Swk  (1-ri)Wchip, i = 1..Nrow • And0 wjwmax , j = 1..Ndecap • ri is the occupancy ratio of row i Cell Decap wj ISPD'02, San Diego, CA

  8. Solver – Sequential Quadratic Programming (SQP) • QPSOL - Quasi-Newton method to solve the problem of multidimensional minimization of functions with derivatives • Requirements • evaluation of the objective function and constraint functions • calculation of first-order derivatives ISPD'02, San Diego, CA

  9. x(t)and – nodevoltages, source currents, inductor currents u(t) – time-dependent sources i() – current sources applied to all bad nodes + Adjoint Sensitivity Analysis • Original circuit Vj(t) • Adjoint circuit ij() ISPD'02, San Diego, CA

  10. Adjoint Sensitivity Analysis (cont’d) • Convolve to get sensitivities Z is thenoise metric for all the grid = S z(j) ISPD'02, San Diego, CA

  11. N linear segments M linear segments Adjoint Sensitivity Analysis (cont’d) • Fast convolution for piecewise linear waveforms ~O(N+M) p q ISPD'02, San Diego, CA

  12. Sensitivity w.r.t. Decaps • Adjoint sensitivity w.r.t. Cnear, R and Cfar • Applying chain rule to find the sensitivity w.r.t. decap width w: ISPD'02, San Diego, CA

  13. Scheme • Analyze circuit and store waveforms • Compute Z • Setup current sources for adjoint circuit • Analyze adjoint circuit & store waveforms • Compute Z/Ci and Z/wi • Evaluate constraint function & gradients • Feed to QP solver to get the updated wi • According to the new wi , replace cells and decaps one by one ISPD'02, San Diego, CA

  14. Start from equal distribution of decaps: • Iteration 1: • Iteration 2: Decap Optimization Process(one row for illustration) ISPD'02, San Diego, CA

  15. Chip Opt Num bad nodes Num of nodes Vmax (V) Z (Vns) Num of dcps Num of rows CPU time (mins) 1 Before After 105 2 974 0.193 0.176 0.121 0.000 1964 53 0.9 2 Before After 80 63 861 0.230 0.196 0.366 0.063 3288 85 15.2 3 Before After 100 70 828 0.222 0.201 0.649 0.200 3664 132 12.5 Optimization Results Vdd=1.8V, vdroplimit =10%Vdd, ri = 80% ISPD'02, San Diego, CA

  16. VDD and GND Contour (chip2) Vmax=0.191V Vmax=0.190V Vmax=0.196V Vmax=0.230V Z=0.366(V•ns) Z=0.063(V•ns) ISPD'02, San Diego, CA

  17. Optimal Placement (chip2) ISPD'02, San Diego, CA

  18. Noise Reduction Trend (chip2) ISPD'02, San Diego, CA

  19. Conclusion • Proposed a scheme of decoupling capacitor sizing and placement for standard-cell layouts • Applied after placement and before signal routing • Formulated into nonlinear programming problem • Reduced transient noise • Presented a fast piece-wise linear waveform convolution for adjoint sensitivity analysis ISPD'02, San Diego, CA

  20. Thank you! ISPD'02, San Diego, CA

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