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Run-time flexibility in FPGAs (Opportunities and Challenges)

Run-time flexibility in FPGAs (Opportunities and Challenges). Trial Lecture Mohamed Ezzat El-Hadedy Aly The Norwegian Center of Excellence for Quantifiable Quality of Service in Communication Systems (Q2S) Norwegian University of Science and Technology (NTNU). Outline of the talk (1/2).

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Run-time flexibility in FPGAs (Opportunities and Challenges)

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  1. Run-time flexibility in FPGAs (Opportunities and Challenges) Trial Lecture Mohamed Ezzat El-Hadedy Aly The Norwegian Center of Excellence for Quantifiable Quality of Service in Communication Systems (Q2S) Norwegian University of Science and Technology (NTNU) Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  2. Outline of the talk (1/2) • Introduction • Reconfigurable Computing • Run-time (FPGA) Basics • FPGA Reconfiguration Modes • Run-time Reconfiguration Categories • Run-time Reconfiguration Tools for Xilinx FPGAs • Run-time Reconfiguration Applications • Advantages of Run-time Reconfiguration

  3. Outline of the talk (2/2) • Partial Run-time Reconfiguration Challenges • Opportunities • Ongoing research • Conclusion

  4. Introduction Hardware reconfiguration is allowed during execution of an application Design A Design A Design B Design B FPGA Chip Design C Design C Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  5. Introduction Groestl Hash Function Keccak Hash Function Blake Hash Function Skein Hash Function JH Hash Function SHA-256 Hash Function

  6. Introduction FPGA Definition • Field-Programmable Gate Arrays (FPGAs) are a recent kind of programmable logic devices. They allow the implementation of integrated digital electronic circuits without requiring the complex optical, chemical and mechanical processes used in a conventional chip fabrication • FPGAs can be embedded in traditional system design flows to perform prototyping and emulation tasks. In addition, they also enable novel applications such as configurable computers with hardware dynamically adaptable to a specific problem • FPGA: Circuits that can be modified or configured by an end-user Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  7. Block RAMs Block RAMs FPGA Structure Introduction Configurable Logic Blocks I/O Blocks Block RAMs Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  8. Introduction Basic CLB structure The basic building block of a Configurable Logic Block • Four slices are grouped by pairs, and each pair is organized in a column with independent carry chain • Configurable switch matrix: There are connections between the horizontal and vertical routing resources to allow signals to change their routing direction Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  9. Introduction Basic LC structure LUT Look Up Tables (LUT) are the kind of logic that is used in SRAM based FPGAs. Basically, each LUT is a collection of single bit memory cells storing individual bit values in each of the cells Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  10. Introduction I/O Blocks IOBs provide a bidirectional programmable interface between the output and the internal structure of the FPGA device Routing possibilities for an I/O Blocks • Input signal • Output signal • High impedance signal Each signal has two storage elements that can be used as registers or latches Block RAM The BRAM is a configurable memory module that attaches to a variety of BRAM interface controllers [1]. The BRAM can be used to store big amounts of data Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges [1] Xilinx, "IP Processor Block RAM (BRAM)", DS444, Ver. 1.00a, March, 2011.

  11. Reconfigurable Computing CPU Flexibility FPGA ASIC Performance, cost, development time Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  12. Reconfigurable Computing Standard Definition : Computation using hardware that can be adapted at the logic level to solve specific problems. CPU Computing Computation performed by executing instructions. Why is reconfigurable computing interesting • Some applications are poorly suited to microprocessors. • VLSI “explosion” provides increasing resources. Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  13. FPGA Reconfiguration Modes Static Reconfiguration Traditional FPGA architectures are primarily statically programmed devices, allowing only one configuration to be loaded at a time • Compile-time Reconfiguration • One configuration per application • System must be halted and then restarted with new program • Most common approach Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  14. FPGA Reconfiguration Modes Dynamic Reconfiguration Whereas static reconfiguration allocates logic for the duration of an application, dynamic reconfiguration (often referred as run-time reconfiguration) uses a dynamic allocation scheme that re-allocates hardware at run time (i.e. during execution of the application) • The physical hardware is smaller than the sum of required resources. • With dynamic reconfiguration we can swap the number of configurations in and out of the actual hardware, as they are needed Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  15. FPGA Reconfiguration Modes context 1 context 2 context 3 AES PCI AES PCI 3DES PCI SHA-512 SHA-1 SHA-1 Single Context [2] • One configuration at a time • Context switching time in order of milliseconds • Programming using a serial bit-stream • High overhead for small configuration changes • Not suitable for run-time reconfiguration [2] Compton, C., Hauck, S. (2000). An Introduction to Reconfigurahle Computing. IEEE Computer (April 2000). Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  16. FPGA Reconfiguration Modes Multi-Context [2] • Multiple memory bits for each programming bit location • Context switching time in order of nanoseconds • Multiplexed set of single context devices • One context can be reprogrammed when another is active A multi-context device has multiple layers of programming bits, where each layer can be active at a different point in time Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  17. FPGA Reconfiguration Modes Partial Reconfiguration [2] • Addresses are used to specify the target location of the configuration data • Allows reconfiguration of only a part of a device while the rest of the device executes. • Reduces the amount of data that must be transferred to the FPGA Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  18. FPGA Reconfiguration Modes Module A ICAP Module C disabled Module A Module A Controller (Microblaze) Flash controller Module B disabled Module B Module B Module C Module C PR Architecture Example Battery FPGA disabled enabled JTAG Base system configuration Bitstreams storage enabled External I/O Reconfigurable area Module A request Static area 1. System controller does not need to be placed in an external device 2. Access to fast Internal Configuration Access Port (ICAP – 32 bits, 100 MHz) 3. Smaller partial bitstreams 4. No need to halt complete system when reconfiguring a module 5. Time multiplexing of FPGA resources, load and unload HW modules on demand

  19. FPGA Reconfiguration Modes Pipeline Reconfiguration [3] • The device consists of independently configurable pipeline stages • Each stage is ready to execute immediately after its programming • Used in data-path style computations [3] H. Schmit, “Incremental Reconfiguration for Pipelined Applications,” Proceedings of the IEEE Symposium on FPGAs jiir Custom Comnputing Muchines (FCCM), p. 47-55, 1997 Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  20. FPGA Reconfiguration Modes Pipeline Reconfiguration (Data–path style) Time t2 t1 t3 t4 t5 Configure 1 Exec.1 Exec.1 Configure 4 Exec. 4 Configure 2 Exec.2 Exec.2 Configure 1 Stages Configure 3 Exec.3 Exec.3 Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  21. Run-time Reconfiguration Categories Algorithmic Reconfiguration [4] • The goal is to reconfigure the system with a different computational algorithm that implements the same functionality, but with different performance, accuracy, power, or resource requirements • Adapts dynamically to environmental or operational changes Changing the control algorithm from being 2nd order to 3rd order. [4] Neema S., et al, “Adaptive Computing and Runtime Reconfiguration,” Proceedings of the 1999 Military and Aerospace Applications of Programmable Devices and Technologies Conference, September 1999. Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  22. Run-time Reconfiguration Categories Architectural Reconfiguration [4] • The goal is to modify hardware topology by reallocating resources to computations Corr. Filters Corr. Filters DSP DSP IFFT IFFT X X FFT FFT FPGA FPGA PSR DSP DSP Extract ROI Extract ROI PSR Post Proc. * * Conv. Filters Conv. Filters Post Proc. [4] Neema S., et al, “Adaptive Computing and Runtime Reconfiguration,” Proceedings of the 1999 Military and Aerospace Applications of Programmable Devices and Technologies Conference, September 1999.

  23. Run-time Reconfiguration Categories Functional Reconfiguration[4] • Reconfigure the programmable device with different configurations to execute different functions over time • Eliminating redundant hardware DSP DSP Band-pass Band-pass Band-pass Band-pass FPGA FPGA Limiter DSP DSP Low-pass Low-pass [4] Neema S., et al, “Adaptive Computing and Runtime Reconfiguration,” Proceedings of the 1999 Military and Aerospace Applications of Programmable Devices and Technologies Conference, September 1999. Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  24. Run-time Reconfiguration Categories Fast Configuration • Reconfiguration time is non- productive time • Reconfigure the device as fast as possible in order to minimize reconfiguration overhead Techniques for fast reconfiguration • Configuration prefetching • Configuration compression • Relocation and Defragmentation • Configuration caching Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  25. Fast Configuration Configuration Prefetching [5] • Loading a configuration onto a device in advance, in order to overlap reconfiguration with useful computation Configuration Prefetching issues [5] • Can be exploited if configuration can be done concurrently with computations • Requires prediction which configuration will be needed in next couple of milliseconds • Gets complicated when multiple branches exist in program Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges [5] Pawel Chodowiec, «Run-time Reconfiguration state of the ar», George Mason University

  26. Fast Configuration Configuration Compression [5] • Minimize the amount of data that must be loaded to the device in multi-context environment • Additional decompression circuits must be put on the FPGA die Configuration Caching [5, 6] • Reducing the amount of configuration data that must be transferred to the device • Use fast cache near reconfigurable hardware [6] K. Compton and S. Hauck, “Reconfigurable Computing: a Survey of System and Software,” ACM Computing Surveys, pp. 171-210, vol. 34, no. 2, June 2002. Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  27. Fast Configuration New configuration c5 c5 c1 c3 c1 Relocation / defragmentation c2 c3 c2 c4 c4 Relocation and Defragmentation [5] • Loading and uploading configurations fragments free space • May reconfigure any part of the device • Configurations most likely occupy contiguous areas • Relocation needed if fragmentation of a free space prevents loading new configurations Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  28. Run-time Reconfiguration Tools for Xilinx FPGAs Xilinx ISE [7, 8] • Partially configurable circuits can be implemented using Modular Designs • Special macros and constraints must be applied to partially reconfigurable circuits • Xilinx recommends using modular designs with simple circuits only [7] Altera, White paper, «FPGA Run-Time Reconfiguration: Two Approaches», March 2008, ver 1.0. [8] S. A. Guccione, D. Levi, and P. Sundararajan, “Jbits: A java-based interface to fpga hardware,” in Proceedings of the 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), 1999. Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  29. Run-time Reconfiguration Tools for Xilinx FPGAs JBits [7] • JBits is a set of Java classes which provides an API to access the Xilinx FPGA bitstream • A bitstream can be produced by Xilinx design tools or read back from actual hardware • JBits API are low-level functions for direct manipulation of all configuration details • JBits require good knowledge of the FPGA • May be used as a basis for other tools More about Jbits? • Where to get it? • http://www.xilinx.com/labs/projects/jbits/ • A tutorial: • http://www.hopsys.com/whitepaper.html • http://www.klabs.org/richcontent/MAPLDCon99/.../p27_sundararajan_s.ppt Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  30. Run-time Reconfiguration Tools for Xilinx FPGAs Tools Based on JBits • JRTR [9] • Direct and simplified support for RTR designs • XVPI [10] • Hardware/Software Interface • BoardScope [11] • Chip debug tool • VirtexDS (Device Simulator) [12] • Full simulation of runtime reconfigurable system possible • Simulates the reconfiguration • Jroute [13] • Automatic routing [9] Scott McMillan and Steven A. Guccione. Partial run-time reconfiguration using JRTR. In Reiner W. Hartenstein and Herbert Gruenbacher, editors, Field-Programmable Logic and Applica- tions, pages 352{360. Springer-Verlag, Berlin, August 2000. Proceedings of the 10th Interna- tional Workshop on Field-Programmable Logic and Applications, FPL 2000. Lecture Notes in Computer Science 1896.

  31. Run-time Reconfiguration Tools for Xilinx FPGAs Design Tools • PlanAhead • Xilinx floorplanning tool • Available on: http://www.xilinx.com/tools/planahead.htm • ReCoBus-Builder • Easy usable builder for Reconfigurable systems • Available on: www.recobus.de Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  32. Run-time Reconfiguration Tools for Xilinx FPGAs [10] Sundararajan, P and S. A. Guccione, “XVPI: A Portable Hardware / Software Interface for Virtex,” Reconfigurable Technology: FPGAs for Computing and Applications II, Proc. SPIE 4212, pp. 90-95, Bellingham, WA, November 2000. [11] D. Levi and S. A. Guccione, “BoardScope: A Debug Tool for Reconfigurable Systems,” In John Schewel, ed., Configurable Computing Technology and its Use in High Performance Computing, DSP, and Systems Engineering, Proc. SPIE Photonics East, Bellingham WA, pp. 239-346, 1998. [12] S. P. McMillian, B. J. Blodget, and S. A. Guccione. VirtexDS: A device simulator for Virtex. In Reconfigurable Technology: FPGAs for Computing and Applications II, Proceedings of SPIE, volume 4212, pages 50–56, Bellingham, Washington, November 2000. [13] E. Keller. JRoute: a run-time routing API for FFGA hardware. In Seventh Reconfigurable Architectures Workshop (RAW 2000), Cancun, Mexico, May 2000. Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  33. Applications for non-frequent reconfiguration [14] Run-time reconfiguration applications • Rapid prototyping, • Searching (text, genetic database) • Mode changing (test equipment, radio) • Self-repair / self-optimizing Applications for high-speed reconfiguration (area saving) [14] • Networking (exchange packet filters according to traffic) • Modulation/frequency/encryption hopping in military radios Applications for high-speed reconfiguration (acceleration) [14] • Crypto (e.g. asym. crypto for key exchange & symmetric for data) [14] Dirk Koch: Partial Runtime Reconfiguration for Industrial Applications  – Methods and Tools, Talk at the FPGA-forum in Trondheim (Norway) Feb. 2010. Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  34. Evolvable Hardware Systems Run-time reconfiguration applications • Evolving Artifical Neural Networks • Evolvable Hardware Platforms • Partial reconfiguration would allow to test different possible combinations • Fuzzy systems • Modular Robotics (Yet Another Modular Robot (YaMoR unit) • More details : http://lslwww.epfl.ch/~upegui/docs/DPR.pdf Signal Processing/Image Processing Systems • JPEG Encoder/Decoder systems • Edge detection applications Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  35. Advantages of Run-time Reconfiguration Run-time Reconfiguration benefits [7]: • Reduced power consumption • Hardware reuse (E.g reduced memory requirements) • Obsolescence avoidance • Flexibility • Reduced time to reconfigure • Application Portability • In Partial Reconfiguration only the reconfigured partial run time (PRR) is stalled while static region and other PRRs continue operating • Smaller bitstreams sizes Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges [7] Altera, White paper, «FPGA Run-Time Reconfiguration: Two Approaches», March 2008, ver 1.0.

  36. Advantages of Run-time Reconfiguration Obsolescence avoidance [7] One of the most touted advantages of FPGAs in military designs is the ability to “future proof” applications through the careful application of hardware and software design, and the careful use of third-party application program interfaces (APIs) and design applications Application Portability [7] One of the goals of a run-time configurable system is to encapsulate the reconfigurable system into a portable application or avionics pod Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges [7] Altera, White paper, «FPGA Run-Time Reconfiguration: Two Approaches», March 2008, ver 1.0.

  37. Partial Run-time Reconfiguration (PRR) Challenges Xilinx PR Implementation Flow Manual steps HDL Design Description PRR Challenges [15] • Complicated design flow • Requires manual intervention and knowledge about target device • Can decrease the performance of the system as compared to full configuration if system design is not carefully considered HDL Synthesis Set Design Constraints Placement Analysis Implement Static Design and PR Modules Merge Final Bitsreams [15] Shaon Yousuf, Ann Gordon-Ross, «RunTime FPGA Partial Reconfiguration for Image Processing Applications», University of Florida - PPT Presentation

  38. Module A ICAP Module C Controller (Microblaze) Flash controller Module B Modules: A and B PRR 1 Static modules PRR 2 Modules: C Current PR Design Flow [16] Partial Run-time Reconfiguration (PRR) Challenges • Steps • Partition the system into modules • Define static modules and reconfigurable modules • Decide the number of PR regions (PRRs) • Decide PRR sizes, shapes and locations • Map modules to PRRs • Define PRR interfaces, instantiate slice macros for PRR interfaces • Optimization problems • Design partitioning • Number of PRRs • PRR sizes, shapes and locations • Mapping PRMs to PRRs • Type and placement of PRR interfaces Design partitioning Design floorplanning and budgeting Static modules Reconfigurable Modules (PRMs) FPGA Static region 2 # of PRRs 1 [16] Chris Conger, Ann Gordon-Ross, and Alan D. George , «Design Framework for Partial Run-Time FPGA Reconfiguration», University of Florida, ERSA, 2008.

  39. Partial Run-time Reconfiguration (PRR) Challenges PRR Challenges • There is no robust documented design methodology to guide a user through the implementation of the reconfiguration region [7]. • Large bitsream • Reconfiguration costs large amount of energy • Commercial tool support is limited • Security issues • Virus scan of configured hardware is not easy because • Bit-files change on every synthesis process run • Configured hardware has to be reread into a bit-file • Scanner has to simulate the hardware • Reconfigurable hardware itself can be reconfigurable Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges [7] Altera, White paper, «FPGA Run-Time Reconfiguration: Two Approaches», March 2008, ver 1.0.

  40. Opportunities • Provide High level algorithms to hardware • Improve the exist commerical tools to increase the efficiency from differents aspects • Power consumption • Area • Speed • Reduce the configuration time • Develop, implement and evaluate a novel compilation and synthesis system approach • Develop a smart routing and placement tools to prevent bad configuration Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  41. Ongoing research • Fine-grained Partial Runtime Reconfigurable on Virtex-5 FPGAs (In 18th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Charlotte, North Carolina, USA, May, 2010) • Demonstrates systems based on Virtex-5 series FPGA that provide full support for active partial run-time reconfiguration • The ReCoBus-Builder tool with a special adjusted communication architecture to improve the performance and efficiency, combined with an easy usable design flow Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  42. Ongoing research • Advanced Partial Run-time Reconfiguration on Spartan-6 FPGAs (In Proceedings of the IEEE International Conference on Field-Programmable Technology (ICFPT'10), Beijing, China, December, 2010) • Demonstrates systems based on Spartan-6 series FPGA that provide full support for active partial run-time reconfiguration • Provide new flow design that allows the migration of modules among different systems. • Context Switching Reconfigurable Hardware for Communication Systems (COSRECOS) Tool • http://www.mn.uio.no/ifi/english/research/projects/cosrecos/ Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  43. Ongoing research • Routing Optimizations for Component-based Systems Design and Partial Run-time Reconfiguration on FPGAs (In Proceedings of the IEEE International Conference on Field- Programmable Technology (ICFPT'10), Beijing, China, December, 2010.) • Proposed methods to significantly enhance the resource utilization (the strict bounding box constraints) of the FPGA routing fabric • Achieve area and reconfiguration time improvements of up 33% in a run-time reconfigurable system using Xilinx spartan-6 Technology Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

  44. Conclusion Conclusion • Run-time reconfigurable systems utilize reconfigurable hardware better • Hardware and software based techniques can be applied to minimize reconfiguration overhead • Penalty in reconfiguration time • Still, a considerable research effort is onging to improve the tools to provide an ever increasing efficieny and ease of use • Open area for optimization exist for different aspects, such as power consumption, hardware reuse, Flexibility, Reduced time to reconfigure, Application Portability and small bit-stream files Mohamed El-hadedy -- Run-time flexibility in FPGAs - Opportunities and Challenges

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