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TIME BASED ENCRYPTION ON NETWORK PROCESSOR TEAM WOLFDALE The University of Southern California

TIME BASED ENCRYPTION ON NETWORK PROCESSOR TEAM WOLFDALE The University of Southern California. Team Wolfdale Members. Instructor: Dr. Young Cho Mentor : Siddharth Bhargav Team Members Praveen Francis Gaurav Yadav Samitsubhro Banerji Kaushik Raju. The Project.

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TIME BASED ENCRYPTION ON NETWORK PROCESSOR TEAM WOLFDALE The University of Southern California

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  1. TIME BASED ENCRYPTION ON NETWORK PROCESSOR TEAM WOLFDALE The University of Southern California

  2. Team Wolfdale Members Instructor: Dr. Young Cho Mentor : SiddharthBhargav Team Members Praveen Francis GauravYadav SamitsubhroBanerji KaushikRaju

  3. The Project • A Time Based Content EncryptionAlgorithmBased On a Specific Sender-Receiver IP Pairs.

  4. The problems • Encryption at software level is slow as compared to hardware level • Most encryption algorithms use static keys. • HERE we Use a DYNAMIC KEY

  5. The General Concept 12.0.1.3 Data 10.0.1.3 SENDER/RECEIVER IP NO MATCH Data Router on NetFPGA Router on NetFPGA 10.0.1.3 / 12.0.1.3 10.0.1.3 / 12.0.2.3 12.0.2.3 10.0.2.3

  6. The General Concept 12.0.1.3 Data 10.0.1.3 SENDER/RECEIVER IP MATCH Encrypting… SENDER/RECEIVER IP MATCH Decrypting… Encrypted Data Data Router on NetFPGA Router on NetFPGA 10.0.1.3 / 12.0.1.3 10.0.1.3 / 12.0.2.3 12.0.2.3 10.0.2.3

  7. System Flow Chart No Unmodified Packet IP Matcher Packet Yes Source • Processor 1 Destination Timestamp Payload Encrypt/Decrypt • Processor 2 Modified Packet

  8. Multi-threading withbranch ID Stage IF Stage LUT4 Rs_data(1) 1 Taken Rs_data(0) Rt_data(11:0) MUX BS PC BNS 1 101 ADD 0 Control Unit PC Instruction Memory 4K 100 PC BS Reg File 32*8B BNS PC Branch 200 Rs_data(31:0) 300 Rt_data(31:0) Mod4 Counter 50 1 0 BS = Branch if set BNS = Branch if not set

  9. IP Matcher 4 Unit Comparator Block If Found No Match Match 64-bit 64-bit 64 bit IP 64 bit IP Else 64-bit 64-bit Packet Processor and Timestamp Register Source Destination Timestamp Memory Bank 0 Memory Bank 1 Data In Payload Data Out a Data Out a Data Out b Data Out b

  10. ENCRYPTER/DECRYPTER Timestamp from Header E N C R Y P T EN1 DATA_OUT DATA_IN Table of Keys Timestamp Reg EN2 D E C R Y P T DATA_OUT DATA_IN

  11. Multi-core Implementation Encrypt data! Calculating checksum.. Comparing MAC ID.. MAC IDs PF1 OUTPUT QUEUES PF2 PF3 IN FIFO PF4 PF4 PF PF PF PF5 PF5 Arbiter PF6 DONE!! PF7 MATCH!! PF8 IP Matcher Encrypt / Decrypt NO MATCH!! IP Matcher Encrypt / Decrypt PF1 PF2 PF3 PF4 PF4 PF5 PF5 MAC IDs PF6 PF7 PF8

  12. Future Scope Of Work • Use of sophisticated encryption/decryption techniques. • Implementation of bloom filter for ip matcher • Two dummy threads to be used for additional network functionalities.

  13. Evaluation of Project • Evaluation Methods • Secure transmission of data in between nodes • Throughput measurement • Project Results evaluation • logic functionality Check • Bug Analysis • Rectify Design • Compare With The Software Emulation Results

  14. PROGRESS REPORT Phase Description Date Status Single Core Processor with Multi Threading 04/23/2013 Completed Hardware Accelerators Design Simulation 04/23/2013 Completed Multi Core Processor with Multithreading 04/30/2013 In Progress Hardware Accelerators Individual Implementation 05/02/2013 In Progress Integration of Hardware Accelerators with Multicore Processors 05/07/2013 Pending Evaluation of the System 05/10/2013 Pending

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