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CCD-based Pixel Detectors by LCFI

CCD-based Pixel Detectors by LCFI Andrei Nomerotski (U.Oxford) on behalf of LCFI collaboration Hiroshima2006, Carmel Outline LCFI Collaboration Pixel Sensors and their Readout Column-Parallel CCDs Storage Pixels : ISIS Mechanical Studies Summary.

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CCD-based Pixel Detectors by LCFI

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  1. CCD-based Pixel Detectors by LCFI Andrei Nomerotski (U.Oxford) on behalf of LCFI collaboration Hiroshima2006, Carmel Outline • LCFI Collaboration • Pixel Sensors and their Readout • Column-Parallel CCDs • Storage Pixels : ISIS • Mechanical Studies • Summary

  2. LCFI :Linear Collider Flavour Identification Valencia Goals : Development of technologies and algorithms for the ILC vertex detector

  3. Pixel Sensors • Traditionally LFCI develops CCD-based sensors • Builds on successes of the SLD vertex detector which was based on CCDs and arguably was the closest to the required ILC parameters ever built The VXD3 upgrade vertex detector: 96 large CCDs, 307 Million pixels (1996)

  4. Vertex Detector for ILC Main requirements: • Excellent point resolution (3-4 μm), ~1 Gigapixel 20x20 μm • Low material budget ( 0.1% X0 per layer) • Low power dissipation • Moderate radiation hardness ( 20 krad/year) • Tolerance to Electro-Magnetic Interference (EMI) • Operation in 5T magnetic field • Fast Readout – the challenge

  5. 337 ns 0.2 s 2820x 0.95 ms The Challenge LC BeamTime Structure: What readout speed is needed? • If read once per train : occupancy ~200 hits/mm2 : too slow • Need to read once accumulated occupancy ~10 hits/mm2 • => 20 times per train = 50µs/MPixel • Fastest commercial CCDs ~ 1 ms/MPixel • Two approaches • Parallel Readout of traditional CCD: CPCCD – information leaves the sensor as fast as it can • Storage Sensors : each pixel has a ‘memory’ filled up during collisions and read out between trains at slow rate: ISIS technology – information is stored in the sensor = one train

  6. M M N N “Classic CCD” Readout time  NM/fout Column Parallel CCD Readout time = N/fout Column Parallel CCD • Simple idea : read out a vector instead of a matrix  Readout time shortened by orders of magnitude BUT • Despite ‘parallel processing’ readout rate is still challenging : 50 MHz clock moves charge 2500 times in 50 µs. 2500x20 µm = 50 mm • Every column needs own amplifier and ADC  requires readout chip

  7. Column Parallel CCD • Readout Chip is a difficult but clearly feasible problem • Geometrically concept of columns is similar to the silicon strips - strip detectors have complex readout chips integrated in ladder • However density of channels requires bump-bonding • Difference wrt Strips: to move the charge need to clock all columns of the CCD simultaneously • Simple exercise : • typical capacitance of CCD sensor : 100nF • 50MHz  10 ns rise time • Clock current = 100 nF x 2 V / 10 nsec = 20A ! • Voltage drops 20 A x 0.1 Ohm = 2 V • Inductance of 1mm long bond wire = 1 nH : corresponds to 0.3 Ohm at 50 MHz • Driving a full area CPCCD is a major challenge! • Need a special high current clock driver • Need to be extra careful with the design of clock distribution

  8. CPCCD : LCFI R&D Milestones • Established proof of principle for small area sensors : CPC1 • Established proof of principle for readout chip : CPR1, developed and produced more sophisticated CPR2 • Moved on to large area sensors : CPC2 • Need to handle the problem of clock driver • Design dedicated clock driver : CPD1 • Find ways to reduce the CCD capacitance • Find ways to reduce the required clock voltage Next slides: Results from prototypes

  9. Next Generation Sensor: CPC2 No connections this side Clock bus Charge injection Extra pads for clock monitoring and drive every 6.5 mm Image area Four 2-stage SF in adjacent columns Standard Field-enhanced Standard Temperature diode on CCD Four 1-stage and 2-stage SF in adjacent columns Main clock wire bonds Main clock wire bonds CPR1 CPR2 • Standard two phase CCD, 20 micron square pixels • Three different chip sizes with common design: • CPC2-70 : 92 mm  15 mm image area • CPC2-40 : 53 mm long • CPC2-10 : 13 mm long • Compatible with CPR1 and CPR2 • Two charge transport sections: standard and field enhanced • Choice of epitaxial layers for different depletion depth: 100 .cm (25 μm thick) and 1.5 k.cm (50 μm thick)

  10. CPCCD Wafer ISIS1 CPC2-70 CPC2-40 CPC2-10

  11. CPC2: First Results 55Fe spectrum from CPC2-10 at 1 MHz K.Stefanov RAL • First 55Fe spectrum at 1 MHz, -40 C, reset every pixel • Analogue readout (no RO chip) • Noise 65 e- ( typical MIP signal 1600 e-)

  12. Next Generation CPCCD Readout Chip – CPR2 Voltage and charge amplifiers 125 channels each 5-bit flash ADCs Cluster finding logic Sparse readout circuitry FIFO Bump bond pads CPR1 CPR2 • CPR2 designed for CPC2 • Numerous improvements over CPR1 and new test features • Size : 6 mm 9.5 mm • 0.25 μm CMOS process (IBM) • Solder bump bonding CPC2-CPR2 in progress at VTT Wire/Bump bond pads Steve Thomas, RAL Bump-bonded CPC1/CPR1

  13. Clock Drivers for CPC2 Requirements: 2 Vpk-pk at 50 MHz over 40 nF Two Options: Transformer • Planar air core transformers on 10-layer PC • Dimension: 1 cm square IC driver: CPD1 • First CPCCD driver chip (CPD1) submitted in July 2006, ready in October 2006 • CPD1: 2-phase CMOS driver chip for 20 Amp current load at 25 MHz (L2-L5 CCDs) • 0.35 μm process, size  3 x 8 mm2 • 32 W peak power but 0.5% duty cycle • Thermal and electromigration issues seems to be under control

  14. Transformer Drive Tests: CPC2-40 in MB4.0 Transformer CPR1/CPR2 pads Clock monitor pads Johan Fopma, Oxford U • “Busline-free” CCD: the whole image area serves as a distributed busline • Effective inductance minimized through cancellation of magnetic fields from opposite clock phases • 50 MHz achievable with suitable driver • First clocking tests have been done

  15. Next Steps for CPCCD • Evaluate performance of CPC2 bump-bonded to CPC2/CPR2 • Designing with e2V test devices to study how to reduce CCD capacitance and how to reduce clock voltage • Theoretically can achieve factor of 4 reduction in C • 10(H)480(V) pixels, new improved process capabilities at e2V: 0.5 m feature size, ~200 nm blind alignment

  16. Storage Pixels • Industry analogy is “Burst mode” : capturing a limited number of images at short intervals • Burst mode imagers are available commercially (ex. DALSA) with rates up to 100MHz : the rate is limited by the charge transfer between neighboring cells • Memory is implemented as a CCD register associated with an imaging pixel : whatever one can fit in an area of one pixel Dart bursting a ballon : 100 consecutive frames at 1M frame/sec

  17. Storage Pixels as Particle Detectors • ILC requirements : capture charge every 50 us 20kHz – no problem Challenges : • Used as particle detector – need efficient charge collection from the whole area • Need to fit 20 cell CCD register into 20x20 square micron pixel (together with photogate and some logic) • Need a more complicated than pure CCD process

  18. In-situ Storage Image Sensor : ISIS • Charge is collected into a photogate • Each pixel has its own 20-cell CCD register : store raw charge during collisions • Increased resistance to EMI • Column-parallel readout during quiet time at ~1 MHz: much reduced clocking requirements

  19. The ISIS1 Cell • 1616 array of ISIS cells with 5-pixel buried channel CCD storage register each • Cell pitch 40 μm  160 μm, no edge logic (pure CCD process) • Chip size  6.5 mm  6.5 mm Output and reset transistors OG RG OD RSEL Column transistor OUT Photogate aperture (8 μm square) CCD (56.75 μm pixels)

  20. Tests of ISIS1 Tests with Fe-55 source • ISIS1 without p-well tested first and works OK • ISIS1 with p-well has very large transistor thresholds, permanently off – problem understood • Next R&D steps : decrease pixel size, implement practical RO schemes – investigating new vendors K.Stefanov RAL

  21. Mechanical Options Target of 0.1% X0 per layer (100μm silicon equivalent) • Unsupported Silicon • Longitudinal tensioning provides stiffness • No lateral stability • Not believed to be promising • Thin Substrates • Detector can be thinned to epitaxial layer (~20 μm) • Silicon glued to low mass substrate for lateral stability • Longitudinal stiffness still from moderate tension • Beryllium has best specific stiffness • Rigid Structures • Foams look very promising

  22. Beryllium substrate Minimum thickness 0.15% X0 Good qualitative agreement from FEA models and measurement Carbon Fibre substrate Better CTE match than Be ~0.09% X0, no rippling to <200K lateral stability insufficient Silicon Tension Beryllium Glue Be and Carbon Fibre Substrates J.Goldstein

  23. Rigid Structures: Foams • Properties: • Open-cell foam • Macroscopically uniform • No tensioning needed • 3% RVC (Reticulated Vitreous Carbon)prototype • Sandwich with foam core • 0.09% X0 • Mechanically unsatisfactory • 8% ( 4%) Silicon Carbide prototype • Single-sided: substrate + foam • 0.14% X0 • Glue application: glue pillars are better than thin layer 20 µm silicon 1.5 mm silicon carbide

  24. Summary • LCFI is a viable and growing collaboration to develop technologies and algorithms for VD • First generation sensors extensively studied • Column parallel CCD principle proven • First results from the second generation of sensors and readout chips • Detector-scale CCDs • Sparsified readout • Developing advanced clock drivers • First prototypes of storage devices • Mechanics : 0.1% X0ladders seems achievable, foams favoured as sensor support substrates

  25. CPC1/CPR1 Performance 5.9 keV X-ray hits, 1 MHz column-parallel readout Voltage outputs, non-inverting (negative signals) Noise 60 e- Charge outputs, inverting (positive signals) Noise 100 e- K.Stefanov RAL • First time e2V CCDs have been bump-bonded • High quality bumps, but assembly yield only 30% : mechanical damage during compression suspected • Differential non-linearity in ADCs (100 mV full scale) : addressed in CPR2 Bump bonds on CPC1 under microscope

  26. Backup Slides

  27. CPR2 Test Results Sparsified output Test clusters in • Parallel cluster finder with 22 kernel • Global threshold • Upon exceeding the threshold, 49 pixels around the cluster are flagged for readout • Tests on the cluster finder: works! • Several minor problems, but chip is usable • Design occupancy is 1% • Cluster separation studies: • Errors as the distance between the clusters decreases • Reveal dead time • Many of the findings have already been input into the CPR2A design Tim Woolliscroft, Liverpool U Tim Woolliscroft, Liverpool U

  28. Radiation Damage Effects in CCDs: Simulations Simulation at 50 MHz Operating window Signal density of trapped electrons in 2D • Full 2D simulation based on ISE-TCAD developed • Trapped signal electrons can be counted • CPU-intensive and time consuming • Simpler analytical model also used, compares well with the full simulation • Window of low Charge Transfer Inefficiency (CTI) between -40 C and 0 C • Will be verified by measurements on CPC2 L. Dehimi, K. Bekhouche (Biskra U); G. Davies, C. Bowdery, A.Sopczak (Lancaster U)

  29. In-situ Storage Image Sensor (ISIS) 5 μm Global Photogate and Transfer gate • Additional ISIS advantages: • ~100 times more radiation hard than CCDs – less charge transfers • Easier to drive because of the low clock frequency: 20 kHz during capture, 1 MHz during readout • ISIS combines CCDs, active pixel transistors and edge electronics in one device: specialised process • Development and design of ISIS is more ambitious goal than CPCCD • “Proof of principle” device (ISIS1) designed and manufactured by e2V Technologies ROW 1: CCD clocks ROW 2: CCD clocks On-chip switches On-chip logic ROW 3: CCD clocks ROW 1: RSEL Global RG, RD, OD RG RD OD RSEL Column transistor

  30. Silicon Carbide Foam Glue “pillars” (right plot) are better than thin glue layer (left plot)

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