Pulsar firmware status

1. Pulsar firmware status March 12th, 2004 Sakari Pitkänen, Tomi Mansikkala Overall firmware status Pulsar Slink formatter Slink merger Muon Reces SVT L2toTS Transmitters How to keep firmware versions in order

2. Overall firmware status Pulsar pre-processors Muon L1 muon L1 XTRP L1 trigger Merger TS PC T2toTS Cluster SLINK L2 CAL (CLIST/Iso) PreFred SVT SVT Electron ShowMax (RECES) Merger

3. Pulsar Slink formatter • Slink flow control • Handles Slink flow control (link full, link down, user reset) • Creates control words (Beginning Of Fragment, End Of Fragment) • Pulsar Slink frame format • Creates Header and Trailer • Internal Spy FIFO • Saves all data words • Saves Slink control signals and formatter status for each word sent out • Can be read and enabled through VME • Data word counter • Counts number of data words, stamp in the trailer • Send empty package on demand (useful if upstream is unavailable) • Can send out an empty package (no data words, only Header and Trailer)

4. Slink merger AUX Card Slink LSC Slink LDC DataIO FPGA 1 Slink LDC DataIO FPGA 2 Slink LDC Slink LSC P3 Control FPGA Slink LDC • Receives data from four Slink mezzanine cards • Saves data to input DAQ buffers • Merges data and checks mismatch errors and stamps in the trailer • Creates one Slink package for merged data • Saves Slink formatted data to output DAQ buffers • Sends data out from P3 - AUX card - Slink

5. Slink merger Slink dataflow DataIO FPGA 1 Slink input FIFO Output FIFO Control FPGA Input DAQ RAM … … Buffer 0 Buffer 1 DataIO 1 input FIFO L1A FIFO Buffer 2 Merger Buffer 3 Slink input FIFO Output FIFO Slink formatter Input DAQ RAM … Output FIFO … … Buffer 0 Merger Buffer 1 L1A FIFO Buffer 2 … Buffer 3 DataIO 2 input FIFO DataIO FPGA 2 Slink input FIFO Output FIFO … Input DAQ RAM B# … … Output DAQ RAM Buffer 0 Buffer 1 Buffer 0 L1A FIFO Buffer 2 Merger Buffer 3 L1A FIFO Buffer 1 Slink input FIFO Output FIFO Buffer 2 Input DAQ RAM Buffer 3 … … Buffer 0 Buffer 1 L1A FIFO Buffer 2 Buffer 3

6. Slink merger Pulsar Slink frame format Now lower 8 bits for Bunch counter • Merger creates it’s own header and trailer • Data is not modified just merged • (Headers and trailers are kept) Merger trailer Input 4 trailer Slink input 4 data Input 4 header Input 3 trailer Slink input 3 data Input 3 header Input 2 trailer Slink input 2 data Input 2 header Input 1 trailer Slink input 1 data Input 1 header Merger header

7. Muon L1T input AUX Card Slink LSC Hotlink RX DataIO FPGA 1 Hotlink RX DataIO FPGA 2 Hotlink RX Slink LSC Control FPGA Hotlink RX XTRP input P3 • Receives data from four Hotlink mezzanine cards, XTRP input and L1 trigger input • Saves data to input DAQ buffers • Zero suppresses Muon data • Merges data and saves it to output DAQ buffer • Creates one Slink package for merged data • Sends data out from P3 - AUX card - Slink

8. Reces AUX Card Slink LSC Taxi RX DataIO FPGA 1 Taxi RX DataIO FPGA 2 Taxi RX Slink LSC Control FPGA Taxi RX P3 • Receives data from four Taxi mezzanine cards • Saves data to input DAQ buffers • Zero suppresses Reces data (Phase I: no zero suppresion) • Merges data • Creates one Slink package for merged data • Saves Slink formatted data to output DAQ buffer • Sends data out from P3 - AUX card - Slink

9. SVT AUX Card Slink LSC SVT input Slink LSC Control FPGA P3 • Receives SVT data • Saves data to input DAQ buffer • Creates one Slink fragment for SVT data needed for L2 algorithm • Saves Slink formatted data to output DAQ buffer • Sends data out from P3 - AUX card - Slink

10. L2toTS CDF control signals L1A Buffer number L2A L2R L1T input Control FPGA TS For “sparky” trigger (Teststand use) • Waits for L1A and data from L1 trigger input or CPU decision • Adjustable delay for L2 decision to TS • Sends L2A or L2R to TS • Finish handshake with TS and rearm for next event

11. Transmitter firmwares General transmitter End of event Empty event Data bits (In case of Gap or Latency word, used for delay value) • Gap (delay between data words) • Latency(delay before first word sent out) Output FIFO Output interface … … RAM • Output interface varies between different transmitter firmwares • (Hotlink, Taxi) • After L1A a statemachine starts to transfer data from RAM to FIFO • Divided to four buffers • Each output channel has its own RAM • Four control bits

12. How to keep firmware versions in order File structure • One directory for files to configure FPGAs; another for archiving stable versions • Pulsar firmware configuration keeps all development versions and latest stable version • Pulsar firmware archive keeps all stable versions • Files kept • VHDL source code • Files necessary for recreating this version • Readme with revision history • FPGA configuration files the FPGAs • Source code under CVS control

13. How to keep firmware versions in order New version procedure Procedure now carefully followed for every new version