1 / 11

Computer Architecture CST 250

Computer Architecture CST 250. Combinational Circuits Prepared by: Omar Hirzallah. Contents. Combinational Circuits. Designing Procedure Problem with Solution Binary Adders Half Adder & Implementation Full Adder & Implementation. Combinational Circuits:.

asarah
Télécharger la présentation

Computer Architecture CST 250

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Computer ArchitectureCST 250 Combinational Circuits Prepared by: Omar Hirzallah

  2. Contents • Combinational Circuits. • Designing Procedure • Problem with Solution • Binary Adders • Half Adder & Implementation • Full Adder & Implementation

  3. Combinational Circuits: A Circuit whose outputs depend only on the current inputs; hence they appear to combine the inputs in some way to produce the outputs. A combinational circuit consists of input variables, logic gates and output variables. The logic gates accept signals from the inputs and generates signals to the outputs. The combinational circuits are used to build modern computers. A BLOCK diagram & logic diagram of a combinational circuit is shown below: Logic Diagram BLOCK Diagram Designing Procedure: • The designing procedure of CC involves the following steps: • From the specification of the circuit, determine the required no. of inputs and outputs and assign a symbol to each. • Derive the truth table that defines the required relationship between inputs and outputs. • Obtain the simplified Boolean functions for each output as a function of the input variables. • Draw the logic diagram and verify the correctness of the design.

  4. The Problem: Design a combinational circuit to control three doors, as follows: 1. An alarm signal will be activated if more than one door are opened. 2. No alarm signal will be activated if all are closed You are requested to do the following: a. determine the input and output b. drive the truth table c. obtain the logic function and simplify it d. draw the logic diagram Alarm on Alarm off Door A Door B Door C Door A Door B Door C

  5. SOLUTION • Inputs: A, B, C (Three Inputs represents the doors) • Outputs: F (Alarm) c. F = A’BC + AB’C + ABC’ + ABC F = C(A  B) + AB It is simplified using Boolean rules but we can also simplify using K-Map b. d.

  6. Binary Adders : Digital computers perform a variety of information processing tasks. The most basic arithmetic operation is the addition of binary digits. There are basically four possible basic rules for binary addition. Case 1 Case 2 Case 3 Case 4 Bit 1 Bit 2 Sum is 0 Carry is 0 Sum is 1 Carry is 0 Sum is 0 Carry is 1 Sum is 1 Carry is 0 There are two types of binary adders, Half Adder and Full Adder.

  7. HALF ADDER: A combinational circuit that performs the addition of two bits is called a Half Adder. Case 1 Case 2 Case 3 Case 4 Bit 1 Bit 2 Half Adder S C B1 B2 Sum is 0 Carry is 0 Sum is 1 Carry is 0 Sum is 0 Carry is 1 Sum is 1 Carry is 0 Standard Form: SOP S= X’Y + XY’ C= XY Canonical Form: S (X,Y) =  (1,2) C (X,Y) =  (3)

  8. Implementation of Half Adder:

  9. FULL ADDER: A full adder combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs and two outputs. Two of the input variables, denoted by X and Y, represent the two significant bits to be added. The third input Z, represents the carry from the previous lower significant position. S= X’Y’Z + X’YZ’ + XY’Z’+XYZ C= X’YZ + XY’Z + XYZ’ + XYZ The Simplified Expressions: S= X  Y  Z C= XY + XZ + YZ S (X,Y,Z) =  (1,2,4,7) C (X,Y,Z) =  (3,5,6,7) Canonical Form

  10. Implementation of Full Adder in SOP: S= X’Y’Z + X’YZ’ + XY’Z’+XYZ C= XY + XZ + YZ

  11. Implementation of Full Adder with two Half Adders and an OR Gate:

More Related