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Computer Organization

Computer Organization. Lecture Set – 05.2 Chapter 5 Huei-Yung Lin. Outline - Processor Implementation. Overview Single-Cycle Implementation Multi-Cycle Implementation 1. Analyze instruction set; get datapath requirements

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Computer Organization

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  1. Computer Organization Lecture Set – 05.2 Chapter 5 Huei-Yung Lin

  2. Outline - Processor Implementation • Overview • Single-Cycle Implementation • Multi-Cycle Implementation \ 1. Analyze instruction set; get datapath requirements 2. Select datapath components andestablish clocking methodology 3. Assemble datapath that meets requirements 4. Determine control signal values for each instruction 5. Assemble control logic to generate control signals • Pipelined Implementation Computer Organization

  3. Outline - Multicycle Design • Overview \ • Datapath Design • Controller Design • Microprogramming • Exceptions • Performance Considerations Computer Organization

  4. Multicycle Execution - Key Idea • Break instruction execution into multiple cycles • One clock cycle for each major task 1. Instruction Fetch 2. Instruction Decode and Register Fetch 3. Execution, memory address computation, or branch computation 4. Memory access / R-type instruction completion 5. Memory read completion • Share hardware to simplify datapath Computer Organization

  5. Characteristics of Multicycle Design • Instructions take more than one cycle • Some instructions take more cycles than others • Clock cycle is shorterthan single-cycle clock • Reuse of major components simplifies datapath • Single ALU for all calculations • Single memory for instructions and data • But, added registers needed to store values across cycles • Control Unit Implemented w/ State Machine • Control signals no longer a function of just the instruction Computer Organization

  6. (Equivalent to Book Fig. 5.25, p. 318) Multicycle Datapath - High-Level View Computer Organization

  7. Review: Steps in Processor Design 1. Analyze instruction set; get datapath requirements 2. Select datapath components andestablish clocking methodology 3. Assemble datapath that meets requirements 4. Determine control signal values for each instruction 5. Assemble control logic to generate control signals Computer Organization

  8. Review: Register Transfers • Instruction Fetch Instruction <= MEM[PC]; PC = PC + 4; • Instruction Execution Instr.Register Transfers add R[rd] <= R[rs] + R[rt]; sub R[rd] <= R[rs] - R[rt]; and R[rd] <= R[rs] & R[rt]; or R[rd] <= R[rs] | R[rt]; lw R[rt] <= MEM[R[rs] + s_extend(offset)]; sw MEM[R[rs] + sign_extend(offset)] <= R[rt]; PC <= PC + 4 beq if (R[rs] == R[rt]) then PC <- PC+4 + s_extend(offset<<2) else PC <= PC + 4 j PC <= upper(PC)@(address << 2) Key idea: break into multiple cycles! Computer Organization

  9. Multicycle Execution Steps 1. Instruction Fetch 2. Instruction Decode and Register Fetch(and branch target calculation) 3. One of the following: • Execute R-Type Instruction OR • Calculate memory address for load/store OR • Perform comparison for branch 4. Memory access for load/storeOR R-type instruction completion (save result) 5. Memory read completion (save result - load only) Computer Organization

  10. (Book Fig. 5.30, p. 329) Summary - Multicycle Execution • Instructions take between 3 and 5 clock cycles (1) (2) (3) (4) (5) New registers needed to store values across clock steps! Computer Organization

  11. 4 Multicycle Execution Step (1)Instruction Fetch IR = Memory[PC]; PC = PC + 4; PC + 4 Computer Organization

  12. Reg[rs] PC + 4 Reg[rt] Multicycle Execution Step (2)Instruction Decode and Register Fetch A = Reg[IR[25-21]]; (A = Reg[rs]) B = Reg[IR[20-15]]; (B = Reg[rt]) ALUOut = (PC + sign-extend(IR[15-0]) << 2) Branch Target Address Computer Organization

  13. Reg[rs] Mem. Address PC + 4 Reg[rt] Multicycle Execution Steps (3)Memory Reference Instructions ALUOut = A + sign-extend(IR[15-0]); Computer Organization

  14. Reg[rs] R-Type Result PC + 4 Reg[rt] Multicycle Execution Steps (3)ALU Instruction (R-Type) ALUOut = A op B Computer Organization

  15. Branch Target Address Reg[rs] Reg[rt] Multicycle Execution Steps (3)Branch Instructions if (A == B) PC = ALUOut; Branch Target Address Computer Organization

  16. Branch Target Address Reg[rs] Reg[rt] Multicycle Execution Step (3)Jump Instruction PC = PC[31-28] concat (IR[25-0] << 2) Jump Address Computer Organization

  17. Mem. Address Reg[rs] PC + 4 Reg[rt] Multicycle Execution Steps (4)Memory Access - Read (lw) MDR = Memory[ALUOut]; Mem. Data Computer Organization

  18. Reg[rs] PC + 4 Reg[rt] Multicycle Execution Steps (4)Memory Access - Write (sw) Memory[ALUOut] = B; Computer Organization

  19. Reg[rs] R-Type Result PC + 4 Reg[rt] Multicycle Execution Steps (4)ALU Instruction (R-Type) Reg[IR[15:11]] = ALUOUT Computer Organization

  20. Reg[rs] Mem. Address PC + 4 Mem. Data Reg[rt] Multicycle Execution Steps (5)Memory Read Completion (lw) Reg[IR[20-16]] = MDR; Computer Organization

  21. (Book Fig. 5.30, p. 329) Summary - Multicycle Execution • Instructions take between 3 and 5 clock cycles Computer Organization

  22. (Equivalent to Book Fig. 5.27, p. 322 without ALU control) Full Multicycle Datapath Computer Organization

  23. (Equivalent to Book Fig. 5.28, p. 323) Full Multicycle Implementation Computer Organization

  24. Review: Steps in Processor Design 1. Analyze instruction set; get datapath requirements 2. Select datapath components andestablish clocking methodology 3. Assemble datapath that meets requirements 4. Determine control signal values for each instruction 5. Assemble control logic to generate control signals Computer Organization

  25. Multicycle Execution Step (1)Fetch IR = Memory[PC]; PC = PC + 4; 1 1 0 0 0 X 010 0 X 1 0 1 Computer Organization

  26. Multicycle Execution Step (2)Instruction Decode and Register Fetch A = Reg[IR[25-21]]; (A = Reg[rs]) B = Reg[IR[20-15]]; (B = Reg[rt]) ALUOut = (PC + sign-extend(IR[15-0]) << 2) 0 0 X 0 0 X 010 X X 0 0 3 Computer Organization

  27. Multicycle Execution Steps (3)Memory Reference Instructions ALUOut = A + sign-extend(IR[15-0]); 0 0 X 1 0 X 010 X X 0 0 2 Computer Organization

  28. Multicycle Execution Steps (3)ALU Instruction (R-Type) ALUOut = A op B 0 0 X 1 0 X ??? X X 0 0 0 Computer Organization

  29. Multicycle Execution Steps (3)Branch Instructions if (A == B) PC = ALUOut; 0 1 if Zero=1 X 1 0 X 011 1 X 0 0 0 Computer Organization

  30. Multicycle Execution Step (3)Jump Instruction PC = PC[21-28] concat (IR[25-0] << 2) 0 1 X X 0 X XXX 2 X 0 0 X Computer Organization

  31. Multicycle Execution Steps (4)Memory Access - Read (lw) MDR = Memory[ALUOut]; 0 0 1 X 0 X XXX X X 1 0 X Computer Organization

  32. Multicycle Execution Steps (4)Memory Access - Write (sw) Memory[ALUOut] = B; 0 0 1 X 1 X XXX X X 0 0 X Computer Organization

  33. Multicycle Execution Step (4)ALU Instruction (R-Type) Reg[IR[15:11]] = ALUOut; (Reg[Rd] = ALUOut) 0 0 X X 0 1 XXX X 1 0 1 X Computer Organization

  34. Multicycle Execution Steps (5)Memory Read Completion (lw) Reg[IR[20-16]] = MDR; 0 0 X X 0 0 XXX X 0 0 1 X Computer Organization

  35. Review: Steps in Processor Design 1. Analyze instruction set; get datapath requirements 2. Select datapath components andestablish clocking methodology 3. Assemble datapath that meets requirements 4. Determine control signal values for each instruction 5. Assemble control logic to generate control signals Computer Organization

  36. Full Multicycle Implementation Computer Organization

  37. Multicycle Control Unit • Review: single-cycle implementation • All control signals can be determined by current instruction + condition • Implemented in combinational logic • Multicycle implementation is different • Control signals depend on • current instruction • which clock cycle is currently being executed • Implemented as • Finite State Machine (FSM) OR • Microprogrammed Implementation - “stylized FSM” Computer Organization

  38. Inputs Outputs Current State Next State Review - Finite State Machines • What’s in the Finite State Machine • Combinational Logic • Storage Elements (Flip-flops) Computer Organization

  39. Review - Finite State Machines • Behavior characterized by • States - unique values of flip-flops e.g., “101” • Transitions between states, depending on • current state • inputs • Output values, depending on • current state • inputs • Describing FSMs: • State Diagrams • State Transition Tables Computer Organization

  40. ARM’ + ARM•DOOR’ = ARM’ + DOOR’ ARM•DOOR IDLE BEEP Honk=1 ARM ARM arm honk ARM’ WAIT door clk fclk = 1Hz Review - State Diagrams • "Bubbles" - states • Arrows - transition edges labeled with condition expressions • Example: Car Alarm Computer Organization

  41. ARM’ + ARM•DOOR’ = ARM’ + DOOR’ ARM•DOOR IDLE BEEP Honk=1 ARM ARM ARM’ WAIT State Transition Table • Transition List - lists edges in State Diagram PS Condition NS Output IDLE ARM' + DOOR' IDLE 0 IDLE ARM*DOOR BEEP 0 BEEP ARM WAIT 1 BEEP ARM' IDLE 1 WAIT ARM BEEP 0 WAIT ARM' IDLE 0 Computer Organization

  42. State Machine Design • Traditional Approach: • Create State Diagram • Create State Transition Table • Assign State Codes • Write Excitation Equations & Minimize • Modern Approach • Enter FSM Description into CAD program • Synthesize implementation of FSM Computer Organization

  43. FSM Control Unit Implementation • FSM Inputs: • Clock • Instruction register op field • FSM Outputs: control signals for datapath • Enable signals: Register file, Memory, PC, MDR, and IR • Multiplexer signals: ALUSrcA, ALUSrcB, etc. • ALUOp signal - used for ALU Control as in single-cycle implementation Computer Organization

  44. Transition from previous state (conditioanl) State name (Op=‘LW’) Memory access 3 MemRead IorD = 0 Enable signal Multiplexer signal Transition to next state (unconditioanl) Describing Controller Function in State Diagrams - Conventions • Enable Control Signals • Asserted (true) in a state if they appear in the state bubble • Assumed Deasserted (false) in a state if they do not appear in the state bubble • Multiplexer/ALU Control Signals • Asserted with a given value in a state if they appear in a state bubble • Assumed Don’t Care if they do not appear in the state bubble • See Figures 5.32 - 5.36 Computer Organization

  45. Multicycle Control - Full State Diagram Computer Organization

  46. Instruction Fetch Instruction Decode / Register Fetch State 0 State 1 Start (Op = ‘LW’ or Op = ‘SW’) (OP = ‘R-Type’) (OP = ‘BEQ’) (OP = ‘J’) State 8 Branch State State 9 Jump State State 2 Mem. Ref States State 6 Execution States Control FSM - Instruction Fetch / Decode States MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCWrite PCSource = 00 ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Computer Organization

  47. from State 1 (OP = ‘LW’ OR OP = ‘SW’) State 2 Memory Address Computation (OP = ‘SW’) (OP = ‘LW’) Memory Access State 5 State 3 Memory Access Write-back step State 4 to State 0 Control FSM - Memory Reference States ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 MemWrite IorD = 1 MemRead IorD = 1 RegWrite MemToReg=1 RegDst = 0 Computer Organization

  48. from State 1 (OP = R-Type) Execution State 6 R-type completion State 7 to State 0 Control FSM - R-Type States ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 RegDst = 1 RegWrite MemtoReg = 0 Computer Organization

  49. from State 1 (OP = ‘BEQ’) Branch Completion State 8 to State 0 Control FSM - Branch State ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 Computer Organization

  50. from State 1 (OP = ‘J’) Jump Completion State 9 to State 0 Control FSM - Jump State PCWrite PCSource = 10 Computer Organization

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