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Design and development of a reconfigurable cryptographic co-processor

Design and development of a reconfigurable cryptographic co-processor. Daniele Fronte. Superviseur industriel : Eric Payrat. Directeur de thèse : Annie Pérez. Soutenance de thèse Marseille, 8 Juillet 2008. Sommaire. Introduction Cahier des charges et objectifs Choix des algorithmes

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Design and development of a reconfigurable cryptographic co-processor

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  1. Design and development of areconfigurable cryptographic co-processor Daniele Fronte Superviseur industriel : Eric Payrat Directeur de thèse : Annie Pérez Soutenance de thèse Marseille, 8 Juillet 2008

  2. Sommaire • Introduction • Cahier des charges et objectifs • Choix des algorithmes • Coprocesseur • Architecture • Exécution de micro-instructions • Résultats • Validation FPGA • Synthèse ASIC • Conclusions

  3. Cahier des charges du Coprocesseur • Cryptographie • Multi-algorithmes • Systèmes embarqués • Sécurité • Cellules standards d’Atmel • Puces - Lecteurs de cartes à puce

  4. Choix • Cryptographie • Clé secrète? • Clé publique? • Multi-algorithmes • Algorithmes standards/propriétaires • Multi-algorithmes • Quel degré de reconfigurabilité? • FPGA ou pas de FPGA? • Systèmes embarqués • Taille • Performances • Sécurité • Attaques latérales de canal: SPA, DPA…

  5. DES DES, AES • Cryptographie à clé secrète Alice Bob DES-1

  6. DES Message en clair L R 32 32 • Taille du bloc données : 64 bits • Taille initiale de la clé : 56 bits • Permutation Initiale • 16 boucles : • Fonction F • Ou exclusif • Permutation finale IP L0 R0 F F 16 boucles F F L16 R16 32 32 FP Message encrypté

  7. Détails de DES Fonction F : • Expansion E • Ou exclusif • Sbox • Permutation P R Clé 32 48 E 48 S1 S2 S3 S4 S5 S6 S7 S8 32 P 32

  8. AES • Taille du blocs données : 128 bits • Taille initiale de la clé : 128, 192, 256 bits • 10 boucles, dont 8 avec : • Sbox • ShiftRows • MixColumns • AddRoundKeys

  9. Détails de AES Transformations : • Sbox • ShiftRows • MixColumns • AddRoundKeys

  10. Détails de AES Transformations : • Sbox • ShiftRows • MixColumns • AddRoundKeys

  11. Détails de AES Transformations : • Sbox • ShiftRows • MixColumns • AddRoundKeys

  12. Détails de AES Transformations : • Sbox • ShiftRows • MixColumns • AddRoundKeys

  13. SHA • Fonction de Hachage input 000 001 010 SHA SHA SHA 8AEFB06C 426E07A0 A671A1E2 588B4858 D694A730 E193A01E CF8D30AD 0AFFEFD3 32CE934E 32FFCE72 47AB9979 443FB7ED 1C193D06 773333BA 7876094F Hash sum

  14. Utilisation de SHA Message 517F3AB6 Alice Condensé SHA Si oui, le message est authentique et intègre =? Message, condensé 517F3AB6 Bob Message SHA Condensé

  15. Détails de SHA-256 • Taille du blocs données : (multiple de) 512 bits • Taille du condensé : 256 bits 64 boucles : • 8 variables: A, B, … , H • 4 Fonctions: Ch, Maj, Σ0, Σ1 • 64 valeurs temporaires Wt • Ou exclusif Wt Ch Kt Σ1 Maj Σ0

  16. Opérations requises AES DES SHA

  17. Coprocesseur Cryptographique Reconfigurable = Celator • krypton, encrypt, crypto etc.  déjà utilisés ! • Cryptographie en grecque : • Kriptós = cacher • Gràfo = écrire • Cryptographie en latin • Celare = cacher

  18. Architecture de Celator

  19. Réseaux systoliques de processeurs Input data streams Processing Elements : • Grain fin • Grain gros • 1D, 2D, 3D PE PE PE PE PE PE PE PE Input data streams Input data streams PE PE PE PE PE PE PE PE Input data streams

  20. Construisons un Processing Element array Data matrix Systolic Processor Network

  21. PE Array, Controller PE PE PE PE Data Bus Control Bus PE PE PE PE PE PE PE PE Processing Element PE PE PE PE Controller

  22. PE Array, Controller, CRAM Reconfigurabilité donnée par : • Réseau systolique de Processing Elements • CRAM Controller PE Array CRAM

  23. Vue générale du système Celator ARM 7 TDMI AHB CRAM PE Array Programs and Data IF Controller Main Memory Other Peripherals

  24. Interface Advanced High-performance Bus (AHB) HSEL_RAM HWRITE HWDATA [31:0] HRDATA [31:0] HSEL_REG HADDR [ 11: 0] Split Address reg Data/controls From/to CRAM Data/controls From/to Controller Control reg Status reg interrupt CPU_clock Celator_clock

  25. PE array northern data I/O PE array 32-bits MUX_N PE00 PE01 PE02 PE03 PE10 PE11 PE12 PE13 PE array western data I/O 32-bits 32-bits PE array eastern data I/O PE20 PE21 PE22 PE23 PE30 PE31 PE32 PE33 MUX_E MUX_W MUX_S 32-bits PE array southern data I/O

  26. Exemple d’exécution • Remplissage de la CRAM • Lecture des micro-instructions • AES Shift Rows

  27. Système interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  28. Remplissage de la CRAM interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  29. Remplissage de la CRAM interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA AES-1 Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  30. Remplissage de la CRAM interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller AES-2 32 HRDATA AES-1 Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  31. Remplissage de la CRAM interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller AES-3 AES-2 32 HRDATA AES-1 Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  32. Remplissage de la CRAM interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller AES-4 AES-3 AES-2 32 HRDATA AES-1 Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  33. Remplissage de la CRAM interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM DATA-3 HADDR 12 DATA-2 Address CPU 12 DATA-1 AES-7 Address Controller AES-6 AES-5 CRAM AES-4 AES-3 AES-2 32 HRDATA AES-1 Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  34. Démarrage de Celator interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  35. Lecture des micro-instructions interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA AES-1 Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  36. Chargement des données dans le PE array interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Data 1 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  37. Chargement des données dans le PE array interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Data 2 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  38. Chargement des données dans le PE array interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Data 3 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  39. Chargement des données dans le PE array interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM Data 4 HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  40. AES Shift Rows

  41. AES Shift Rows interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  42. AES Shift Rows interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  43. AES Shift Rows interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  44. AES Shift Rows interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  45. AES Shift Rows interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  46. AES Shift Rows interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  47. AES Shift Rows interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  48. AES Shift Rows interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  49. AES Shift Rows interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

  50. AES Shift Rows interface Di Controller Di CPU CPU 32 32 Split Address reg 32 CRAM HADDR 12 Address CPU 12 Address Controller 32 HRDATA Do CPU 32 32 Control reg Do Controller HWDATA 32 PE in 32 Status reg 32 6 6 6 6 PE Array status out Status in Control out Control in PE out 32 Controller Reg Y Reg X

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