1 / 16

ABC130 testing

ABC130 testing. Bruce Gallop and Peter Phillips 15 Jan 2014. FIB. Enable on transmit is inverted Fixed Data and XOFF direction Now works with Direction = 1 Received packets tested Register read L1 data Trivial R3 (empty data). FIB repair by NanoScope (Bristol ).

azriel
Télécharger la présentation

ABC130 testing

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ABC130 testing Bruce Gallop and Peter Phillips 15 Jan 2014

  2. FIB • Enable on transmit is inverted • Fixed Data and XOFF direction • Now works with • Direction = 1 • Received packets tested • Register read • L1 data • Trivial R3 (empty data)

  3. FIB repair by NanoScope (Bristol) FIB repair to XOFFR (short enable to VDD) FIB repair to DATAR (short enable to GND) CHIP FIB2

  4. XOFF fix seen close up: M3 accessed, not yet modified

  5. XOFF fix seen close up: Enable line cut, shorted to VDDD

  6. DC measurementof DATA and XOFF • For this chip, DATAR is permanently enabled as a driver (as expected). • Following pages refer to output from DATAR when dir=1 (for dir=0 it does not work)

  7. Example (decoded) packets • ST [44] abc130_ReadRegs() • Configuring stream 14 • Variable 10022 unknown to ABC130 configure • op: d008 seq: 33 len: 739 • Stream: 8 • Format: 100 • DatSrc: 0 • [No. : chip type L0:BC StpBt : StripData (as per type) ] • 000 : 20 8:Reg 00:00 0 : 00000000 • 007 : 20 8:Reg 01:00 0 : 00000000 • 019 : 20 8:Reg 02:00 0 : 1f000000 • 031 : 20 8:Reg 03:00 0 : 00000000 • 043 : 20 8:Reg 07:00 0 : 00000000 • 061 : 20 8:Reg 10:00 0 : 00000000 • 073 : 20 8:Reg 11:00 0 : 00000000 • 085 : 20 8:Reg 12:00 0 : 00000000 • 097 : 20 8:Reg 13:00 0 : 00000000 • 109 : 20 8:Reg 14:00 0 : 00000000 • 121 : 20 8:Reg 15:00 0 : 00000477 • 133 : 20 8:Reg 16:00 0 : 00000000 • 145 : 20 8:Reg 17:00 0 : 00000000 • 157 : 20 8:Reg 18:00 0 : e042b039 • 169 : 20 8:Reg 19:00 0 : 8a502842 • 181 : 20 8:Reg 1a:00 0 : c0969d22 • op: d008 seq: 34 len: 739 • Stream: 8 • Format: 100 • DatSrc: 0 • [No. : chip type L0:BC StpBt : StripData (as per type) ] • 000 : 20 8:Reg 1b:00 0 : 9822010f • 012 : 20 8:Reg 1c:00 0 : db8ab15b • 024 : 20 8:Reg 1d:00 0 : c3212180 • 036 : 20 8:Reg 1e:00 0 : c08c4843 • 048 : 20 8:Reg 1f:00 0 : c4310180 • 060 : 20 8:Reg 20:00 0 : 00001f10 • 072 : 20 8:Reg 21:00 0 : 00000777 • 084 : 20 8:Reg 22:00 0 : 0000000f • 096 : 20 8:Reg 23:00 0 : 00000000 • 108 : 20 8:Reg 30:00 0 : 00000000 • 120 : 20 8:Reg 31:00 0 : 00000000 • 132 : 20 8:Reg 32:00 0 : 0000001b • 144 : 20 8:Reg 3f:00 0 : 00000000

  8. Tune configuration (Use MUX to tune to nominal values) • Delay DelStepVThrVCalCalPol • 0 3 72 34 0 • BVREF BIREF B8REF COMBIAS • 11 10 10 9 • BIFEED BIPRE LDOD LDOA • 8 17 0 0 • Power at 1.3V, LDO set for minimum drop • Gives 1.24 on VDDD, VDDA

  9. How a scan works • Series of triggers with different configurations • Setup configuration • Each trigger • Send L0 • Send L1 (with appropriate L0ID) • Driven by software, no optimisation • About 1ms between L0 and L1 • 10s ms between triggers • Loop over cal-line (ie 0001, 0010, 0100, 1000)

  10. Single Channel mask scanshowing mask bit ordering in 2 banks of 128 Mask bit Channel decoded from packet

  11. Trig Delay Scanadjusting timing of L0 with respect to CAL Polarity 0 112 Polarity 1 120 => Spacing consistent with cal pulse 8 wide. Reading 3BC, no 01 detect.

  12. First look at Gain – polarity 0 1.2fC 30 2.4fC 65 35 counts -> 80.5mV -> 67 mV/fC (design value 90 mV/fC)

  13. 3-point gain polarity =0 (preliminary) • preamp feed gain (DAC counts) mv/fC noise • 17 8 27.4 63.0 347 • 15 8 27.7 63.7 443 • 19 8 28.1 64.6 349 • 10 8 27.6 63.5 437 • 17 10 27.4 63.0 642 • 17 6 29.1 66.9 432 • 0 8 28.8 66.2 450 • 31 8 28.2 64.9 443 • 17 0 34.7 79.8 379 • 17 13 25.6 58.9 470 • 17 31 19.2 44.2 584

  14. 3-point gain plots Gain (DAC counts per fC)

  15. Summary • Lots more to test • More thorough R3 testing • Trims • Tuning LDO • Another chip may be helpful - Is gain of FIB2 typical or not?

  16. Backup: MUX measurements MUX0 TEST_TRDAC0 428   7310  10318  1341f  160c   88e   96 -> leave here MUX1 TEST_VR0   338   4710   6118   741f   86b   52  -> leave here MUX2 TEST_IR0   338   4710   6118   741f   860a   50 -> leave here VR=1F  VR=10  VR=08  VR=0a  VR=0c  VR=0b MUX6  VCS   978    933    851    881    903    893 MUX7  VCD   404    548    633    611    590    601 MUX8  VCSP  398    542    627    605    584    595 MUX9  VBASE 773    571    444    476    508    492 MUX10 VB    715    516    402    430    459    445 • MUX3 TEST_R8B0   338   4710   6118   741f   860a   50 -> leave here • MUX4 TEST_IPRE0    878    10310   12018   1351f   14911   122 -> leave here • MUX5 TEST_IFEED0    188    30 -> leave here10   4318   551f   659   36 -> leave here • MUX11 - bandgap 620mV (nominal 592). • MUX12 CALLINE00  620  2140  3660  5280  68a0  84c0  100e0  116ff  132 • MUX13 TEST_THDAC00  520  2140  3660  5280  68a0  83c0  99e0  114ff  129 • TESTCOM0   258   3510  4418  541f  63

More Related