Error Injection & Correction : An Efficient Formal Logic Restructuring Algorithm

1. Error Injection & Correction : An Efficient Formal Logic Restructuring Algorithm Ching-Yi Huang, Daw-Ming Lee, Chun-Chi Lin, and Chun-Yao Wang Department of Computer Science, National TsingHua University, Taiwan

2. Outline • Introduction • Overview • The Proposed Approach • Experimental Results • Conclusion

3. Introduction • In the logic synthesis process, gate-level design is often restructured to achieve different optimization objectives • Existing approaches to logic restructuring can be classified into two categories: • Redundancy Restructuring • Error Injection-based Restructuring

4. Introduction • Redundancy Restructuring approaches: • Node merging [14]15] • Rewriting [21] • Redundancy Addition and Removal (RAR) [5] • [5] “Theory of Wire Addition and Removal in Combinational Boolean Networks”, Microelectronic Engineering’07. • [14] “Fast Node Merging With Don’t Cares Using Logic Implications”, TCAD’10. • [15] “Logic Restructuring Using Node Addition and Removal”, TCAD’12. • [21] “DAG-Aware AIG Rewriting: A Fresh Look at Combinational Logic Synthesis”, DAC’06.

5. Introduction • Error Injection-based Restructuring approaches • Rewiring Using Irredundancy Removal and Addition (IRRA) [19] • ATPG/Diagnosis-based Design Rewiring (ADDR) [25] • Error Cancellation Rewiring (ECR) [32] • [19] “Rewiring Using IRredundancy Removal and Addition”, DATE’09. • [25] “Design Rewiring Using ATPG”, TCAD’02 • [32] “ECR:A Low Complexity Generalized Error Cancellation Rewiring Scheme”, DAC’10.

6. Features • The proposed Error Injection & Correction (EIC) belongs to the Error Injection-based Restructuring approach • The EIC can directly remove, add, or replace a desired irredundant target wire/gate, and rectify the erroneous functionality due to this removal, addition, and replacement by adding the rectification networks

7. Contributions • EIC is the first error-injection based restructuring technique that can simultaneously deal with removal, addition, and replacement of wires/gates • Doesn’t need a verification procedure • The EIC can be served as a logic perturbation engine combined with other logic optimization engines to further optimize the circuit

8. Outline • Introduction • Overview • The Proposed Approach • Experimental Results • Conclusion

9. Error Injection & Correction • Error Injection-based Restructuring is a problem where: • Given: • The original circuit Cori • An injected error that is modeled by a set of error effects Ee = {e1, e2, …, ei} • We add the rectification networks which can be also modeled by another set of error effects Er= {ei+1, ei+2, …, en} • Crec = Cori + Ee+ Er, and the combined error effects Ee+Er = {e1, e2, …, en} become redundant to Cori

10. Error Injection & Correction • Logic design errors are functional mismatches between the specification and the implementation a a b b c c a a b b c c a a b b

11. Error Injection & Correction Injected error : wire removal PO1 PO2 error effect

12. Error Injection & Correction Injected error : wire removal PO1 Incorrect PO2 error effect error effect error effect error effect error effect error effect error effect

13. Error Injection & Correction Rectification networks PO1 PO2 error effect error effect error effect error effect error effect error effect error effect

14. Outline • Introduction • Overview • The Proposed Approach • Experimental Results • Conclusion

15. The Proposed Approach • The problem • Where to add the rectification network for the error? • What to add into the rectification network for the error? • How to construct the corrected function with the rectification networks at the selected locations

16. The Proposed Approach (where) Ⅱ Ⅰ Ⅲ error effect . . . . . .

17. The Proposed Approach (what) • Definition 3: Given a Boolean network, an error effect, and a destination gate gd in the TFOC of the error effect, • The Definite ON-set network (DON) at gd is defined as the network having the on-set minterms that change from the on-set of a good circuit to the off-set of a faulty circuit (1/0), and having the don’t-care set of minterms that are in the on-set of both good and faulty circuits • The Definite OFF-set network (DOFF) at gd is defined as the network having the on-set minterms that change from the off-set of a good circuit to the on-set of a faulty circuit (0/1), and having the don’t-care set of minterms that are in the offset of both good and faulty circuits

18. The Proposed Approach (what) a b b (a) (b) a 1/0 b DON = a b -> a (c) (d)

19. The Proposed Approach (how) • Theorem 1: Given a Boolean network, one or more than one destination gate gd, and the error effects at gd, if the error effect propagated to gd is • 0/1: the corrected function for the error effect isgd · DOFF • 1/0 : the corrected function for the error effect isgd + DON • If both 1/0 and 0/1 are propagated to gd, the corrected function for the error effects is either (gd + DON) · DOFF or (gd · DOFF) + DON 0/1 0/1, 1/0 a a g1 g1 0/1, 1/0 0/1 g2 g2 b b c c a 1/0 0/1 g1 1/0 g2 b c DON DON DOFF DOFF 0/1 -> 0/0 1/0 -> 1/1

20. The Proposed Approach (how) • Activating assignment a a b b (a) (b) a 1/0 b 0/1 activating assignments (DON) : a b activating assignments (DOFF) : a (or b) (c) (d)

21. The Proposed Approach (how) • Propagating assignment activating assignment : a activating assignment : a controlling error effect g2 DOFF = a g1 bc bc 0/1 b a a a a g1 0/1 g2 b c Include don’t care = Ignore c noncontrolling error effect g2 DON =ac g1 bc bc b a a a 0/1 1/0 a g1 1/0 g2 b 1 c propagating assignment : c= 1

22. The Proposed Approach (how) • Derivation of DON and DOFF • (a) Region I and II • assignment = activating assignments + propagating assignments • DON/DOF = AND(assignment) (Theorem 2) activating assignment : a DON =AND(assignment) = a ． c noncontrolling error effect g1 bc b a a 0/1 1/0 a g1 1/0 g2 b 1 c propagating assignment : c= 1 a g1 g2 b ac c

23. The Proposed Approach (how) • Derivation of DON and DOFF • (b) Region III • There is more than one path from the error location to gd • Enumerating all the propagating assignments in all propagating paths within the fanout-reconvergent region is not practical Ⅱ error effect Ⅰ Ⅲ . . . . . . gd fanout-reconvergent region

24. The Proposed Approach (how) • Derivation of DON and DOFF • (b) Region III • 1) Outside the fanout-reconvergent region • Activating assignment • Propagating assignment • AND(assignment) • 2) Within the fanout-reconvergent region • DON = AND(assignment) · gdg(assignment) • DOFF = AND(assignment) · gdg(assignment) (Theorem 3) • Corrected function • 0/1 error effect at gd: gd’ = gd · DOFF • 1/0 error effect at gd: gd’ = gd + DON • Both 0/1, 1/0: gd’ = (gd + DON) · DOFF or (gd · DOFF) + DON

25. Outline • Introduction • Overview • The proposed Approach • Experimental Results • Conclusion

26. Experimental Results • C language • ABC environment • 3.0 GHz Linux platform (CentOS 4.6) • Benchmarks: LGSynth93 and IWLS 2005 suite • Optimization engines: Node merging ( NMG ) , Node addition and Removal ( NAR ), and resyn2 script in ABC • Comparison (highly optimized results): • (resyn2 + NMG + NAR )×30 = optimization×30 • Perturbation and optimization: • optimization×5+(EIC×5+optimization×5)×5 • EIR : the target wire/gate, the injected error type, and the destination gate, were randomly selected

27. Experimental Results table5.blif

28. ours Original

29. Conclusion • This paper presents a fast formal logic restructuring technique, EIC, through the process of injecting errors first and then correcting them. • The EIC offers opportunities to the logic restructuring, and it can be served as a logic perturbation engine to further optimize the area of highly optimized circuits. • Our future work is to integrate this work with other optimization engines to reach different objectives, e.g., power, delay, or reliability of the VLSI circuits.

30. Thank you