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指導教授 : 林志明 教授 學生 : 黃世一

Phase Frequency Detectors for Fast Frequency Acquisition in Zero-dead-zone CPPLLs for Mobile Communication Systems.

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指導教授 : 林志明 教授 學生 : 黃世一

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  1. Phase Frequency Detectors for Fast Frequency Acquisitionin Zero-dead-zone CPPLLs for Mobile Communication Systems Kun-Seok Lee; Byeong-Ha Park; Han-il Lee; Min Jong Yoh;Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European16-18 Sept. 2003 Page(s):525 - 528 Digital Object Identifier 10.1109/ESSCIRC.2003.1257188 指導教授 : 林志明 教授 學生 : 黃世一

  2. Outline • Abstract • Introduction • Conventional PFD Circuits • Proposed PFD Circuit • Simulation and Measurement Results • Conclusion • References

  3. Abstract • A new-type PFD for CPPLLs • Reset part and delay part • Input signal edge data, an added delay to remove dead-zone, are not lost • Do not output the wrong information, faster locking property • Reduced frequency acquisition time by about 30% • 0.5μm BiCMOS

  4. Introduction • PLLs in microprocessors and digital signal processors for clock generation circuits, and as a reference signal for wireless communication systems. • PFD, the input reference signal and the divided VCO output signal, produces an output signal proportional to the phase and frequency difference between them.

  5. Faster operating frequency, dead-zone problems, and locking time • Faster frequency acquisition • Separate the reset part and the delay part • Corrects the clock transition overrides occurring during an added delay to prevent the dead-zone

  6. Conventional PFD Circuits

  7. (a) Incorrect output generation due to delay. (b) Incorrect output generation due to the reset signal RST.

  8. Characteristic of the ideal PFD Characteristic of the nonideal PFD

  9. Proposed PFD Circuit

  10. Characteristic of the proposed PFD

  11. Simulation and Measurement Results Simulated characteristics of the conventional (a) and the proposed PFDs (b)

  12. Charge variation in the charge-pump output during the frequency acquisition

  13. Simulated frequency acquisition

  14. Chip photograph of the proposed and conventional PFDs

  15. Measured locking time

  16. Conclusion • Incorrect output generation in the conventional PFD due to the delay element in the feedback path • new-type PFD corrected the wrong information and reduced the locking time • Reset part and delay part

  17. References • Kun-Seok Lee; Byeong-Ha Park; Han-il Lee; Min Jong Yoh;Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European16-18 Sept. 2003 Page(s):525 - 528 Digital Object Identifier 10.1109/ESSCIRC.2003.1257188

  18. Thank You For Your Attention !

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