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Review: Fan-In Considerations

EE534 VLSI Design System Summer 2004 Lecture 12:Chapter 7 &9 Transmission gate and Dynamic logic circuits design approaches. D. C. B. A. C 3. C 2. C 1. C L. Review: Fan-In Considerations. A. B. Distributed RC model (Elmore delay)

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Review: Fan-In Considerations

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  1. EE534VLSI Design SystemSummer 2004 Lecture 12:Chapter 7&9Transmission gate andDynamic logic circuits design approaches

  2. D C B A C3 C2 C1 CL Review: Fan-In Considerations A B Distributed RC model (Elmore delay) TpHL=0.69[R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1+R2+R3+R4)CL] tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. C D

  3. Review: tp as a Function of Fan-In quadratic function of fan-in tp (psec) tpHL tp tpLH linear function of fan-in fan-in • Gates with a fan-in greater than 4 should be avoided.

  4. V DD A B A B C D Review: Influence of Fan-In and Fan-Out on Delay • Fan-out: Number of Gates connected to the output • in static CMOS, there are two gate capacitances per Fan-out • Fan-in: Number of independent variables for the logic function, which has a quadratic effect on tp due to: • resistance increasing • capacitance increasing C D

  5. C3 C2 C1 CL Fast Complex Gates: Design Technique 1 • Transistor sizing • as long as fan-out capacitance dominates • Progressive sizing Distributed RC line M1 > M2 > M3 > … > MN (the MOSFET closest to the output should be the smallest) InN MN In3 M3 In2 M2 Can reduce delay by more than 20%; decreasing gains as technology shrinks In1 M1 Resistance of M1(R1) N times in the delay Equation. The resistance of M2(R2) appears N-1 times etc.

  6. C2 C1 C1 C2 CL CL Review : Fast Complex Gates: Design Technique 2 • Input re-ordering • when not all inputs arrive at the same time critical path critical path 01 charged charged 1 In1 In3 M3 M3 1 1 In2 In2 M2 discharged M2 charged 1 In3 discharged In1 charged M1 M1 01 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL

  7. D C B A C3 C2 C1 CL Review: Sizing and Ordering Effects 3 3 3 3 A 4 4 = 100 fF B 4 5 Progressive sizing in pull-down chain gives up to a 23% improvement. Input ordering saves 5% critical path A – 23% C 4 6 D 4 7

  8. Review: Fast Complex Gates: Design Technique 3 • Alternative logic structures F = ABCDEFGH

  9. Ratioed Logic Ratioed logic is an attempt to reduce The number of transistors required to implant a given logic function, often at the cost of reduced robustness and extra power dissipation

  10. Ratioed Logic

  11. Review: Load Lines of Ratioed Gates

  12. Other logic styles • Transmission gate logic • Pass-transistor logic • NMOS transistors used as switches • Other variants: • Complementary pass-transistor logic (CPL) • Swing-restored pass-transistor logic

  13. Transmission Gate Logic • NMOS and PMOS connected in parallel • Allows full rail transition – ratioless logic • Equivalent resistance relatively constant during transition • Complementary signals required for gates • Some gates can be efficiently implemented using transmission gate logic = =

  14. Transmission Gates (pass gates) Use of transistors as switches are called transmission gates because switches can transmit information from one circuit to another.

  15. CMOS Transmission Gate • A CMOAS transmission gate can be constructed by parallel combination of NMOS and PMOS transistors, with complementary gate signals. • The main advantage of the CMOS transmission gate compared to NMOS transmission gate is to allow the input signal to be transmitted to the output without the threshold voltage attenuation. CMOS transmission gate

  16. source Drain Drain source Characteristics of a CMOS Transmission gate • Case I: If  =VDD, , VI=VDD, and VO is initially zero. In NMOS transistor, under above Condition, terminal ‘a’ acts as the drain and terminal ‘b’ acts as the source. For the PMOS, device terminal ‘c’ acts as the drain and terminal ‘d’ acts as the source. In order to charge the load capacitor, current enters the NMOS drain and the PMOS source. The NMOS gate to source voltage is, VGSN =  - VO = VDD - VO this implies that VGSN continuously change. And for PMOS source-to-gate voltage is VGSP = VI -  = VDD – 0 = VDD This implies that VGSP remains constant. Charging path

  17. Characteristics of a CMOS Transmission gate (Cont.) • When VO=VDD-VTN,VGSN=VTN, the NMOS transmission gate cuts off and IDN=0. However, PMOS transistor continue to conduct, because VGSP of the PMOS is a constant (VGSP=VDD). In PMOS transistor IDP=0, when VSDP=0, which would be possible only, if, VO = VI = 5V This implies that a logic ‘1’ is transmitted unattenuated through the CMOS transmission gate in contrast to the NMOS transmission gate. NMOS transmission gate

  18. Characteristics of a CMOS Transmission gate (Cont.) • Case II: If VI = 0,  = VDD, VO=VDD initially. terminal ‘a’ acts as a source and terminal ‘b’ acts as a drain. For the PMOS transistor terminal ‘c’ acts as a source and terminal ‘d’ acts as a drain. In order to discharge the capacitors current enter the NMOS drain and PMOS source. The NMOS gate to source voltage is, And PMOS source to gate voltage is When VSGP=VO=|VTP|, PMOS transistor cutoff and iDP=o However, since VGSN=VDD, the NMOS transistor continue conducting and capacitor completely discharge to zero. Finally, VO=0, which is a good logic 0. discharging path drain source drain source

  19. Equivalent Resistance Model • For a rising transition at the output (step input) • NMOS sat, PMOS sat until output reaches |VTP| • NMOS sat, PMOS lin until output reaches VDD-VTN • NMOS off, PMOS lin for the final VDD – VTN to VDD voltage swing

  20. Equivalent Resistance – Region 1 • NMOS sat: • PMOS sat: • NMOS sat, PMOS sat until output reaches |VTP| because drain to source voltage is still high

  21. Equivalent Resistance – Region 2 • NMOS sat: • PMOS lin: NMOS sat, PMOS lin until output reaches VDD-VTN

  22. Equivalent Resistance – Region 3 • NMOS off: • PMOS lin: • NMOS off, PMOS lin for the final VCC – VTN to VCC voltage swing

  23. Equivalent resistance • Equivalent resistance Req is parallel combinaton of Req,n and Req,p • Req is relatively constant • This property of CMOS TG is quite desirable

  24. TG equivalent resistor model

  25. Delay in Transmission Gate Networks

  26. Delay Optimization Example: 16 cascade minimum size transmission gates with resistance of 8K C=3.6fF for low to high transition. The delay is given by Use of long pass transistors chains causes significant delay degradation What could be the possible solution to minimize this delay?

  27. Break the chain and insert buffers The insertion of the buffer inverters reduces the delay by a factor of almost 2

  28. CMOS transmission gate remains in a dynamic condition. • If VO=VDD, then NMOS substrate to terminal ‘b’ pn junction is reverse biased and capacitor CL can discharge. • If VO=0, then the PMOS terminal c-to-substrate pn junction is reverse biased and capacitance CL can be charge to a positive voltage. • This implies that the output high or low of CMOS transmission gate circuit do not remain constant with time (dynamic behavior).

  29. Dynamic CMOS • Advantages: • Faster – why? • Reduced input load • No switching contention • Less layout area • Disadvantages: • Charge leakage • Charge sharing • Capacitive coupling • Cannot be cascaded • Complicated timing/clocking • Higher power • Lower noise margins clk NMOS network clk Gnd These issues are discussed in chapter 9

  30. TG Applications: Multiplexer (MUX) circuit • Case I: When the input S is logic high Bottom transistor is conducting and output is equal to input B • Case II: When the input S is logic low Bottom Tg turn off and top TG turn on and output is equal to input A

  31. S S TG Multiplexer S F S VDD In2 S F In1 S GND F = !(In1  S + In2 S) In1 In2 S

  32. Transmission Gate XOR B B M2 A A F M1 M3/M4 B B

  33. Example: Full Adder Carry is the critical signal: closest to the output

  34. A Revised Adder Circuit: applying the design techniques to reduce area and delay

  35. Cin B A Sum Cout TG Full Adder

  36. Transmission Gate Full Adder Similar delays for sum and carry

  37. Chapter 9Dynamic logic circuits design

  38. Dynamic CMOS • In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. • fan-in of n requires 2n (n N-type + n P-type) devices • Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. • requires on n + 2 (n+1 N-type + 1 P-type) transistors

  39. Static vs Dynamic Storage • Static storage • preserve state as long as the power is on • have positive feedback (regeneration) with an internal connection between the output and the input • useful when updates are infrequent (clock gating) • Dynamic storage • store state on parasitic capacitors • only hold state for short periods of time (milliseconds) • require periodic refresh • usually simpler, so higher speed and lower power

  40. Evolution from static to dynamic logic gate

  41. Dynamic CMOS • Advantages: • Faster – why? • Reduced input load • No switching contention • Less layout area • Disadvantages: • Charge leakage • Charge sharing • Capacitive coupling • Cannot be cascaded • Complicated timing/clocking • Higher power • Lower noise margins clk NMOS network clk Gnd

  42. Clk Mp ((AB)+C) Out CL A C B Clk Me Dynamic Gate off Clk Mp on 1 Out In1 In2 PDN In3 Clk Me off on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

  43. Conditions on Output • Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. • Inputs to the gate can make at most one transition during evaluation. • Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails.

  44. Properties of Dynamic CMOS Gates • Logic function is implemented by the PDN only • number of transistors is N + 2 (versus 2N for static complementary CMOS) • Full swing outputs (VOL = GND and VOH = VDD) • Non-ratioed - sizing of the devices does not affect the logic levels • Faster switching speeds • reduced load capacitance due to lower input capacitance (Cin) • reduced load capacitance due to smaller output loading (Cout) • no Isc, so all the current provided by PDN goes into discharging CL

  45. Properties of Dynamic Gates, con’t • Power dissipation should be better • consumes only dynamic power – no short circuit power consumption since the pull-up path is not on when evaluating • lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two) • by construction can have at most one transition per cycle – no glitching • But power dissipation can be significantly higher due to • higher transition probabilities • extra load on CLK • PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn • low noise margin (NML) • Needs a precharge clock

  46. Dynamic 4 Input NAND Gate VDD Out In1 In2 In3 In4 f GND

  47. CL Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out A Evaluate VOut Clk Me Precharge Leakage sources Dominant component is subthreshold current

  48. CLK Impact of Charge Leakage • Output settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks • Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage. Out

  49. CL A Solution to Charge Leakage • Keeper compensates for the charge lost due to the pull-down leakage paths. Keeper CLK Mp Mkp !Out A B CLK Me Same approach as level restorer for pass transistor logic

  50. CL Ca Cb Issues in Dynamic Design 2: Charge Sharing Charge stored originally on CL is redistributed (shared) over CL and CA leading to static power consumption by downstream gates and possible circuit malfunction. CLK Mp Out A B=0 CLK Me When Vout = - VDD(Ca / (Ca + CL )) the drop in Vout is large enough to be below the switching threshold of the gate it drives causing a malfunction.

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