Digital Testing: Scan Design

1. Digital Testing: Scan Design Samiha Mourad Santa Clara University

2. Outline • Problems with sequential testing • What is scan • Types of scan • Types of storage devices • Scan Architectures • Cost of Scan • Partial Scan • Stitching flip-flops Copyrights(c) 2001, Samiha Mourad

3. Problems Impeding Testing • Complexity testing sequential circuits due to • feedback loops • Placement of the circuit in a known state • high chance for hazard, essential hazard • Timing problems in general Copyrights(c) 2001, Samiha Mourad

4. What is Scan Design • This DFT technique is used mainly for synchronous circuit represented by the Huffman model presented in Chapter 3 • We assume the use of D-flip-flops only • A mux is placed at the input of each flip-flop in such a way that all flip-flops can be connected in a shift register for one mux selection and to work in normal mode in the other Copyrights(c) 2001, Samiha Mourad

5. A Generalized Huffman Model Copyrights(c) 2001, Samiha Mourad

6. A Generalized Huffman Model Copyrights(c) 2001, Samiha Mourad

7. What is Scan Design • This DFT technique is used mainly for synchronous circuit represented by the Huffman model presented in Chapter 3 • We assume the use of D-flip-flops only • A mux is placed at the input of each flip-flop in such a way that all flip-flops can be connected in a shift register for one mux selection and to work in normal mode in the other Copyrights(c) 2001, Samiha Mourad

8. Possible Scan Scheme Copyrights(c) 2001, Samiha Mourad

9. How Scan DFT Works • The combinational part is partitioned: • Each input to the FF is considered an output to the circuit • each output of the FF is an input to the circuit • Connect the FF in a shift register and test them • Test the combinational part Copyrights(c) 2001, Samiha Mourad

10. Testing the Combinational Part • Repeat until all patterns are applied. • a. Set SE = 1, shift in the initial values on the flip-flops. (These are the signals at the output of the latches for the first test pattern.) • b. SE = 0, apply a pattern at the primary inputs. • c. Clock the circuit once and observe the results at the primary outputs. • d. Clock the circuit M times. • End repeat. Copyrights(c) 2001, Samiha Mourad

11. An Example Copyrights(c) 2001, Samiha Mourad

12. An Example Copyrights(c) 2001, Samiha Mourad

13. Inserting the Muxes Copyrights(c) 2001, Samiha Mourad

14. Test Application Copyrights(c) 2001, Samiha Mourad

15. Types of Storage Devices • Multiplexed input flip-flop • Two-port flip-flop works with two nonoverlapping clocks • Latch-based Scan Design: requires • 2-latches clocked with non-overlapping clocks • 3-latch clocked with three phases Copyrights(c) 2001, Samiha Mourad

16. 2-Port Flip-flops • Port 1D works with CK1 in normal operation mode as well as at the capture mode of testing • Port 2D works with CK2 in shift mode • To avoid essential hazard during testing, CK1 and CK2 are non-overlapping phases. During t, non of them is working Copyrights(c) 2001, Samiha Mourad

17. Clocked Transparent Latches • (a) A D-latch implemented in NAND gates • (b) An extra NAND is added to suppress static hazard • (c) The corresponding Karnaugh map Copyrights(c) 2001, Samiha Mourad

18. Latches versus Flip-flops Copyrights(c) 2001, Samiha Mourad

19. Latch-based Shift Mode • Because of the tranperancy property of the latches shown in the timing diagram of the previous slide • Latches cannot be used in a shift register unless every pairs works in a master-slave fashion as shown above • It is preferable that the two clocks be non-overlapping Copyrights(c) 2001, Samiha Mourad

20. Level-sensitive Latch • The latch works with the 3 phases A, B and C • For normal operation, clocks B and C • For shift operation, clocks B and A • Two-port flip-flop works with two non-overlapping clocks Copyrights(c) 2001, Samiha Mourad

21. Polarity Hold Latch (IBM) Copyrights(c) 2001, Samiha Mourad

22. Scan Design Architectures • Several architectures: • Multiplexed flip-flops design • Level-sensitive scan design • Scan set scan design • Derivative of scan design: • Parallel scan chains • Partial scan Copyrights(c) 2001, Samiha Mourad

23. Level-Sensitive Scan Design • Each flip-flop of the original design is replaced by a polarity hold (an LSSD) latch • The configuration is shown in the next slide • The input of 2D in the first latch is scan-in • The output of the second latch of the last pair is scan-out • Of course here there is no scan control signal as in the muxed design studied earlier • Instead, the three phases A, B, and C operation control the normal and shift modes Copyrights(c) 2001, Samiha Mourad

24. LSSD Copyrights(c) 2001, Samiha Mourad

25. How does LSSD Work? 1. Test the latches. Set A = B = 1. Apply 0 and 1 alternatively at SI. Clock A, then clock B, N times. 2. Initialize. Shift in the initial values on the flip-flops. (These are the signals at the output of the latches for the first test pattern) Copyrights(c) 2001, Samiha Mourad

26. LSSD: Testing Repeat until all patterns are applied. a. Apply a pattern at the primary inputs. b. Clock C; then clock B once and observe the results at the primary outputs. c. Shift out the response Apply the initialization for the next pattern at SI. Clock A, then clock B, M times. Observe at the primary outputs and the SO pins. Copyrights(c) 2001, Samiha Mourad

27. Scan Set Design • An architecture that allows on-line scan testing Copyrights(c) 2001, Samiha Mourad

28. Multiple Scan Chains • Instead of stringing all the flip-flops or the latches in one shift register • Partition them is several chains • The advantages are: • compatible with multiple clock designs • Shorten test application time • Simplify the stitching of the flip-flops • But, may require extra pins Copyrights(c) 2001, Samiha Mourad

29. Multiple Scan Chains Copyrights(c) 2001, Samiha Mourad

30. What & Why Partial Scan Design • To scan only a subset of the flip-flops • The circuit is easier to test by the sequential ATPG. • The area overhead is minimized. • The placement of the flip-flops is such that the interconnects are minimized. • The delays are shortened. Copyrights(c) 2001, Samiha Mourad

31. Partial Scan Design • To scan only a subset of the flip-flops • How to select this subset? • It is an NP-complete problem • Heuristics on graph model to select the minimum vertex set (MVS) to transform the FSM into an acyclic graph Copyrights(c) 2001, Samiha Mourad

32. An Example Copyrights(c) 2001, Samiha Mourad

33. Fault Coverage • To scan only a subset of the flip-flops • How to select this subset? • It is an NP-complete problem • Heuristics on graph model to select the minimum vertex set (MVS) to transform the FSM into an acyclic graph Copyrights(c) 2001, Samiha Mourad

34. Partial Scan Copyrights(c) 2001, Samiha Mourad

35. Possible Implementations Copyrights(c) 2001, Samiha Mourad

36. Scan Chain Order Copyrights(c) 2001, Samiha Mourad

37. The Cost of Scan Design • Area (muxes, extra routing) • Additional I/Os • Performance, delays within the flip-flops • Heat when testing at speed Copyrights(c) 2001, Samiha Mourad

38. Stitching Effect Copyrights(c) 2001, Samiha Mourad