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A High Performance Controller for NAND Flash-based Solid State Disk (NSSD)

Presentation for Meeting Group in DSN Lab. A High Performance Controller for NAND Flash-based Solid State Disk (NSSD). By: Reza Faridmoayer. Supervisor: Dr. Asadi. Sharif University of Technology, Department of Computer Engineering. November 09, 2010. Outline. Introduction

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A High Performance Controller for NAND Flash-based Solid State Disk (NSSD)

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  1. Presentation for Meeting Group in DSN Lab A High Performance Controller for NAND Flash-based Solid State Disk (NSSD) By: Reza Faridmoayer Supervisor: Dr. Asadi Sharif University of Technology, Department of Computer Engineering November 09, 2010

  2. Outline • Introduction • Hardware Architecture • Software Architecture • Performance Results • References

  3. Introduction • The driving forces for reduction the bit cost of NAND Flash memory: • MLC Technology • Migration to lower geometrics • Necessity the following requirements because of a wide range of mobile applications: Fast start-up time Cost efficiency High performance read/write Low-power consumption Reliability

  4. Hardware Architecture • Previous approach based on Multi-Chips solutions Existing multi-chip architecture for NSSD

  5. Hardware Architecture (cont.) • Utilization DRAM as a write buffer as code and data memory • The proposed NSSD hardware architecture through the following figure.

  6. Hardware Architecture (cont.) • Interfacing directly with the Host through IDE standard interface (ATA-5). • Supportability 2 to 16 Giga bit NAND Flash memories • Supportability 2 channels and up to 4-way interleave. • Acceleration the sequential write operation For improving the performance of NSSD. • The utilization of interleaving scheme of multi NAND Flash memory for acceleration • Utilization small size of SRAM for program, data and buffer memory instead of DRAM for reduction power consumption. • Supportability all power modes like active, idle, standby and sleep mode.

  7. Software Architecture (cont.) • The high-level architecture for NSSD software through the following figure. Host and NSSD S/W Structure NSSD FTL Structure

  8. Software Architecture (cont.) • NSSD software consists of three layers: • 1) Host I/F Layer • 2) Flash Translation Layer • 3) NAND I/F Layer • Some of the FTL functions: • 1) Wear-leveling • 2) Bad Block Management • There are two types of bad blocks: • Initial bad blocks • Runtime bad blocks • 3) power-off-recovery

  9. Performance Results • Comparing the performance of NSSD over the commercial HDD through several industry standard third party benchmark tools.

  10. Performance Results (Cont.)

  11. References [1] Bit MICRO Networks. “E-Disk ATA: 2.5” IDE/ATA Flash Disk,” http://www.bitmicro.com [2] SiliconSystems Inc, “SiliconDriveTM,” http://www.siliconsystems.com [3] M-Systems Inc., “IDE/SATA/SCSI FFD,” http://www.m-sys.com [4] J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho, “A Space Efficient Flash Translation Layer for CompactFlash Systems,” IEEE Transactions on consumer Electronics, Vol.48, No.2,PP.365-375, 2002. [5] Samsung Electronics Co., Ltd., NNAD Flash Memory Data Sheet, 2005. [6] Toshiba,”1.8 inch HDD Specification” http://ssd.toshiba.com [7] FutureMark,”PCMark’05,” http://www.futuremark.com/products [8] Microsoft,”BootVis,” http://www.microsoft.com/whde/system/sysperf/fastboot/bootvis.mspx [9] SiSoftware, “Sandra 2005,” http://www.sisoftware.net

  12. THANK YOU ?

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