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ECE2030 Introduction to Computer Engineering Lecture 17: Memory and Programmable Logic

ECE2030 Introduction to Computer Engineering Lecture 17: Memory and Programmable Logic. Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech. Memory. Random Access Memory (RAM) Contrary to Serial Access Memory (e.g. Tape) Static Random Access Memory (SRAM)

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ECE2030 Introduction to Computer Engineering Lecture 17: Memory and Programmable Logic

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  1. ECE2030 Introduction to Computer EngineeringLecture 17: Memory and Programmable Logic Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

  2. Memory • Random Access Memory (RAM) • Contrary to Serial Access Memory (e.g. Tape) • Static Random Access Memory (SRAM) • Data stored so long as Vdd is applied • 6-transistors per cell • Faster • Differential • Dynamic Random Access Memory (DRAM) • Require periodic refresh • Smaller (can be implemented with 1 or 3 transistor) • Slower • Single-Ended • Can be read and written • Typically, addressable at byte granularity • Read-Only Memory (ROM)

  3. Read/Write Block Diagram of Memory N-bit Data Input (for Write) N K-bit address lines Memory Unit K 2k words N-bit per word Chip Enable • Example: 2MB memory, byte-addressable • N = 8 (because of byte-addressability) • K = 21 (1 word = 8-bit) N N-bit Data Output (for Read)

  4. BitLine Static Random Access Memory (SRAM) • Typically each bit is implemented with 6 transistors (6T SRAM Cell) • During read, the bitline and its inverse are precharged to Vdd (1) before set WL=1 • During write, put the value on Bitline and its inverse on Bitline_bar before set WL=1 Wordline (WL) BitLine

  5. Dynamic Random Access Memory (DRAM) • 1-transistor DRAM cell • During a write, put value on bitline and then set WL=1 • During a read, precharge bitline to Vdd (1) before assert WL to 1 • Storage decays, thus requires periodic refreshing (read-sense-write) Wordline (WL) Bitline

  6. Memory Description • Capacity of a memory is described as • # addresses x Word size • Examples:

  7. 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit How to Address Memory 4x8 Memory 2-to-4 Decoder 0 A0 1 2 A1 3 CS Chip Select D6 D4 D2 D0 D7 D5 D3 D1

  8. 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit How to Address Memory 4x8 Memory 2-to-4 Decoder 0 A0=1 1 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 2 A1=0 3 CS Chip Select=1 D6 D4 D2 D0 D7 D5 D3 D1 Access address = 0x1

  9. 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit Use 2 Decoders 8x4 Memory 2-to-4 Decoder Row Decoder 0 A1 1 2 A2 3 CS Tristate Buffer (read) D0 D1 D2 D3 0 1 Chip Select CS 1-to-2 Decoder Column Decoder A0

  10. Output Input En Vdd En Input Output En CMOS circuit Tristate Buffer • Similar to Transmission Gate • Could amplify signal (in contrast to a TG) • Typically used for signal traveling, e.g. bus En Input Output

  11. Bi-directional Bus using Tri-state Buffer Direction (control data flow for read/write) A Input/Output B

  12. 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit Rd/Wr = 0 Read/Write Memory 8x4 Memory 0 A1 1 2-to-4 Row Decoder 2 A2 3 CS D0 D1 D2 D3 0 1 Chip Select = 0 CS 1-to-2 Column Decoder A0

  13. 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit Rd/Wr = 1 Read/Write Memory 8x4 Memory 0 A1 1 2-to-4 Row Decoder 2 A2 3 CS D0 D1 D2 D3 0 1 Chip Select = 1 CS 1-to-2 Column Decoder A0

  14. D7 D6 D5 D4 A19 A19 1Mx4 1Mx4 D3 A18 A18 A17 A17 D2 D1 D0 A0 A0 R/W R/W CS CS CS Building Memory in Hierarchy • Design a 1Mx8 using 1Mx4 memory chips

  15. D3 D2 D1 D0 1-to-2 Decoder 1 A20 0 A19 A19 1Mx4 1Mx4 A18 A18 A17 A17 CS A0 A0 R/W R/W CS CS Building Memory in Hierarchy • Design a 2Mx4 using 1Mx4 memory chips Note that 1-to-2 decoder is the wire itself (or use an inverter)

  16. A19 D7 A18 A19 A19 A19 A19 1Mx4 1Mx4 1Mx4 1Mx4 A18 A18 A18 A18 D6 A17 A17 A17 A17 A17 D5 D4 A0 CS CS CS CS R/W R/W R/W R/W A0 A0 A0 A0 D3 1-to-2 Decoder 1 D2 D1 0 D0 A20 CS Building Memory in Hierarchy • Design a 2Mx8 using 1Mx4 memory chips

  17. Lower Memory Address 0x0A 0x00000000 0xB6 0x00000001 0x41 0x00000002 0xFC 0x00000003 Higher Memory Address 0x0D 0xFFFFFFFF Flat Memory Model Memory Model • 32-bit address space can address up to 4GB (232) different memory locations

  18. Endianness [Danny Cohen 91] • Byte ordering  How a multiple byte data word stored in memory • Endianness (from Gulliver’s Travels) • Big Endian • Most significant byte of a multi-byte word is stored at the lowest memory address • e.g. Sun Sparc, PowerPC • Little Endian • Least significant byte of a multi-byte word is stored at the lowest memory address • e.g. Intel x86 • Some embedded & DSP processors would support both for interoperability

  19. Endianness Examples • Store 0x87654321 at address 0x0000, byte-addressable Lower Memory Address Lower Memory Address 0x87 0x21 0x0000 0x0000 0x65 0x43 0x0001 0x0001 0x43 0x65 0x0002 0x0002 0x21 0x87 0x0003 0x0003 Higher Memory Address Higher Memory Address BIG ENDIAN LITTLE ENDIAN

  20. Memory Allocation (Little Endian) .data .globl declare declare: .align 0 .word 511 .byte 14 .align 2 .byte 14 .word 0x0B1E8143 .align 2 .ascii “GAece” .half 10 .word 0x2B1E8145 .space 1 .byte 52 .align 1 .byte 16 .space 2 .byte 67 0xFF ------ 0x34 e 0 1c 0x01 ------ ------ f 1d 1 0x00 0x10 0x47 1e 2 10 0x00 0x41 3 11 1f 0x0E 0x65 4 20 12 ------ 0x63 0x43 13 5 21 ------ 0x65 6 14 .align N: Align next datum on a 2n byte boundary .align 0: turn off automatic alignment for .half, .word, .float, and .double till the next .data directive .word: 4 bytes .half: 2 bytes .byte: 1 byte .space: 1-byte space .ascii: ASCII code (American Standard Code for Information Interchange) ------ 0x0A 15 7 0x0E 0x00 16 8 0x43 0x45 9 17 0x81 0x81 a 18 0x1E 0x1E b 19 0x0B 0x2B 1a c ------ d 1b

  21. Read Only Memory (ROM) • “Permanent” binary information is stored • Non-volatile memory • Power off does not erase information stored ROM K-bit address lines N-bit Data Output 2k words N-bit per work K N

  22. 32x8 ROM 32x8 ROM 5 8 Each represents 32 wires 0 A4 1 2 A3 5-to-32 Decoder 3 A2 A1 28 29 A0 30 31 Fuse can be implemented as a diode or a pass transistor D1 D0 D7 D6 D5 D4 D3 D2

  23. 0 A4 1 2 A3 5-to-32 Decoder A2 A1 29 A0 30 31 D0 D1 D7 D6 D5 D4 D3 D2 Programming the 32x8 ROM

  24. Example: Lookup Table • Design a square lookup table for F(X) = X2 using ROM

  25. Square Lookup Table using ROM 0 1 X2 3-to-8 Decoder 2 3 X1 4 X0 5 6 7 F1 F0 F5 F4 F3 F2

  26. Not Used = X0 Square Lookup Table using ROM 0 1 X2 3-to-8 Decoder 2 3 X1 4 X0 5 6 7 F1 F0 F5 F4 F3 F2

  27. Square Lookup Table using ROM 0 1 X2 3-to-8 Decoder 2 3 X1 4 X0 5 6 7 F1 F0 F5 F4 F3 F2

  28. Programmable Connections Fixed AND plane (decoder) Programmable OR plane INPUT OUTPUT (Programmable) Read-Only Memory (ROM) Programmable Connections Programmable AND plane Fixed OR plane Programmable AND plane Programmable OR plane F/F INPUT INPUT OUTPUT OUTPUT Programmable Array Logic (PAL) Devices PAL: trademark of AMD, use PAL as an adjective or expect to receive a letter from AMD’s lawyers Programmable Logic Array (PLA) Classifying Three Basic PLDs

  29. Programmable Logic Array (PLA) A Programmable OR Plane B C Programmable AND Plane C C B B A A F2

  30. Example using PLA

  31. AC BC A B C Example using PLA A B C AB C C B B A A F1 F2

  32. PAL Device IO1 IO2 IO1 IO1 A A B B IO1 Programmable AND Plane A IO2 B Fixed OR Plane

  33. PAL Device Design Example IO1 IO1 A A B B C C D D IO1 Not programmed A IO2 B

  34. CPLD and FPGA [Brown&Rose 96] • Complex Programmable Logic Device (CPLD) • Multiple PLDs (e.g. PALs, PLAs) with programmable interconnection structure • Pioneered by Altera • Field-Programmable Gate Array (FPGA) • High logic capacity with large distributed interconnection structure • Logic capacity  number of 2-input NAND gates • Offers more narrow logic resources • CPLD offers logic resources w/ a wide number of inputs (AND planes) • Offer a higher ratio of Flip-flops to logic resources than CPLD • HCPLD (High Capacity PLD) is often used to refer to both CPLD and FPGA

  35. CPLD structure Logic block PLD PLD PLD PLD I/O block PLD PLD PLD PLD Interconnects

  36. FPGA Structure Logic block I/O block Interconnects

  37. FPGA Programmability • Floating gate transistor • Used in EPROM and EEPROM • SRAM-controlled switch  Control • Pass transistors • Multiplexers (to determine how to route inputs) • Antifuse • Similar to fuse • Originally an Open-Circuit • One-Time Programmable (OTP)

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