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Number One

Number One. Tom Bozic Ian Nuber Greg Ramsey Henry Romero Matt Unangst. GITHU Processor. General Purpose 32-bit, pipelined computer processor MIPS-like architecture Reduced instruction set 24-bit address space 22 bits, concatenate with ending 00 32 bit boundaries 16 Registers.

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Number One

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  1. Number One Tom Bozic Ian Nuber Greg Ramsey Henry Romero Matt Unangst

  2. GITHU Processor • General Purpose 32-bit, pipelined computer processor • MIPS-like architecture • Reduced instruction set • 24-bit address space • 22 bits, concatenate with ending 00 • 32 bit boundaries • 16 Registers

  3. Registers • 16 Registers (ease in immediate operations) • 3 Special Purpose • R0 – zero • R14 – stack pointer • R15 – return address

  4. Instruction Set Architecture • First two bits indicate instruction category • Load, store, bra/jump, R-type • 16 bit immediate built into R-type reduces complexity of design • Addressing Modes • Direct • Indirect with Offset • ISA accounts for full address space • NO PC-relative addressing

  5. Instruction Format Load / Store 31 30 29 24 23 20 19 16 15 0 R-Type 31 24 23 20 19 16 15 12 11 0 Bra / Jmp 31 30 29 26 25 24 23 20 19 0

  6. Instructions • Arithmetic • Add • Addi – add immediate • Sub • Subi – subtract immediate • Data Transfer • Ld - load word • St – store word

  7. Instructions • Logic • And • Andi – And immediate • Or • Ori – Or immediate • Nor • Nand • Sll – logic shift left • Slr – logic shift right

  8. Instructions • Branches • Beq – branch equal to zero • Bne – branch not equal to zero • Jumps • Jmp – jump to specified address • Jsr – jump to subroutine • Interrupt handler • Save current PC in register • Nop – No Operation

  9. Datapath Diagram

  10. Functional Units • Register File • ALU • Control Logic • Memory System • Assembler

  11. Hardware • Xilinx XCV300/400/600/800 FPGA • Keep FPGA on board • Make PCB for all off-chip peripherals • Connect two boards together via ribbon cable

  12. Processor I/O • Serial RS232 port • LCD, Monitor outputs • Keypad, Keyboard Inputs

  13. Vital Goals • Implement processor on FPGA in Verilog • Pipelined • Thorough simulation • Complete Assembler • Keypad, LCD I/O • Make PCB with off-chip peripherals • Successfully run assembly program

  14. Extended Goals • On-chip caches (Instruction and data) • C Compiler • Monitor, Keyboard I/O • Multiplier, Divider units • Floating Point Units

  15. Individuals Roles • Tom Bozic • Assembler, control logic, documentation • Ian Nuber • Assembler, control logic, test-program design • Greg Ramsey • ALU, PCB design • Henry Romero • PCB design, Memory system • Matt Unangst • Pipeline implementation (forwarding, rollback) • Register File

  16. Schedule

  17. Risks • PCB issues (signal noise, speed, etc) • Wire wrapping • Pipeline complexity • Design allows for insertion of no-ops to essentially turn machine into multi-cycle machine

  18. Questions?

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