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3. Digital Implementation of Mo/Demodulators

3. Digital Implementation of Mo/Demodulators. DSB. MOD. amp. SSB. DEM. amp. General Structure of a Mo/Demodulator. Single Side Band (SSB) Modulator. MOD. SSB. Implementation using Real Components. SSB. where. Single Side Band (SSB) Demodulator. DEM. LPF.

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3. Digital Implementation of Mo/Demodulators

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  1. 3. Digital Implementation of Mo/Demodulators

  2. DSB MOD amp SSB DEM amp General Structure of a Mo/Demodulator

  3. Single Side Band (SSB) Modulator MOD SSB

  4. Implementation using Real Components SSB where

  5. Single Side Band (SSB) Demodulator DEM LPF

  6. Single Side Band (SSB) Modulator in Discrete Time Modulator Implemented in two stages: Digital Up Converter DUC Analog MOD ZOH DISCRETE TIME CONTINUOUS TIME

  7. Single Side Band (SSB) Demodulator in Discrete Time Demodulator Implemented in two stages: Digital Down Converter DDC Analog DEM ZOH CONTINUOUS TIME DISCRETE TIME

  8. Digital Down (DDC) and UP (DUC) Converters DUC DDC RF Baseband • MHz for voice • GHz for data • kHz for voice • MHz for data Order of magnitude of resampling:

  9. LPF LPF Problem with Large Upsampling Factor if M is large, very small transition region high complexity filter

  10. Problem with Large Downsampling Factor LPF LPF if M is large, very small transition region high complexity filter

  11. Solution: Upsample in Stages In order to make it more efficient we upsample in L stages

  12. i-th Stage of Upsampling

  13. Example: Upsample in One Stage This is not only a filter with high complexity, but also it is computed at a high sampling rate.

  14. Same Example in Three Stages Total Number of operations/sec= a 95% savings!!!!

  15. Downsample in Stages

  16. i-th Stage of Downsampling noise keep aliased noise away from signal

  17. Example: Downsample in One Stage

  18. Same Example in Three Stages Total Number of operations/sec = … a savings of almost 99% !!!

  19. Stages at the Highest Rates highest rates • the highest sampling rates are close to carrier frequencies, thus very high; • properly choose intermediate frequencies to have simple filters at highest rates

  20. Last Stage in UpSampling wide region

  21. First Stage in DownSampling wide region

  22. Very simple Low Pass Filter: the Comb Integrator Cascade (CIC) same!!! “Comb” “Integrator” these two are the same! Notice: no multiplications!

  23. Frequency Response of the Comb Filter …like a comb!

  24. Impulse Response of the CIC interpolating sequence

  25. The CIC in the Time Domain like a discrete time ZOH!

  26. Two Important Identities: The “Noble” Identities Same !!! As a consequence we have one of two “Noble Identities”: Same!!!

  27. Other “Noble” Identity Same !!! As a consequence we have the other of the two “Noble Identities”:

  28. Efficient Implementation of Upsampling CIC Use Noble Identity: Very simple implementation (no multiplications):

  29. Efficient Implementation of Downsampling CIC Use Noble Identity: Very simple implementation (no multiplications):

  30. Frequency Response of the CIC 5 0 -5 only 13 dB attenuation dB -10 -15 -20 -25 0 0.1 0.2 0.3 0.4 0.5 f=F/Fs Not a very good Low Pass Filter. We want a better attenuation in the stopband!

  31. Put M Stages together Frequency Response:

  32. Improved Frequency Response of CIC Filter Resampling Factor N=10 With M=4 or 5 we already get a very good attenuation.

  33. Example: M=4 Stages

  34. Implementation of M Stage CIC Filter: Upsampling Use Noble Identity:

  35. Implementation of M Stage CIC Filter: Downsampling Use Noble Identity:

  36. Problem: DownSampling CIC is Unstable Now we have to be careful: the output of the integrator will easily go to infinity

  37. CIC Implementation. At the p stage: This implies: and

  38. If we use Q bits for the integrators then we need to guarantee Let the input data use L bits: Then: decimation factor input bits number of stages

  39. Application: Software Defined Radio • Definitions: • Software Defined Radio: modulation, bandwidth allocation … all in software • Field Programmable Gate Array (FPGA): reprogrammable logic device which is able to perform a number of operations in parallel. They can process data at a rate of several 100s of MHz • DSP Chip: optimized for DSP operations by some hardwired ops (such as multiplies).

  40. An HF SSB Software Defined Radio by Dick Benson, The Mathworks, 64MHz 15.6kHz 7.8kHz RF IQ AUDIO Rec. Rec. Rec/Tr Trans. Trans. DAC IQ AUDIO RF FPGA DSP Chip

  41. Transmitter: AUDIO I FIR SSB FIR Q DSP Chip Xilinx Library Modules I FIR FIR CIC RF Q FIR FIR CIC FPGA

  42. Receiver: Xilinx Library Modules I RF CIC FIR FIR Q CIC FIR FIR FPGA I FIR AUDIO Q FIR DSP Chip

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