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Chapter 3b: Arithmetic and Logic Unit

Chapter 3b: Arithmetic and Logic Unit. 0010 0011 0111 0110 1010 1111 0000 1101 OR 1001 1010 1000 0101 0001 1011 1010 0011. There is logic to it. and Rd, Rs, Rt Rd <-- Rs • Rt or Rd, Rs, Rt Rd <-- Rs Ú Rt. Note: Bit numbering starts at zero. AND, OR are bitwise logic operations.

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Chapter 3b: Arithmetic and Logic Unit

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  1. Chapter 3b: Arithmetic and Logic Unit

  2. 0010 0011 0111 0110 1010 1111 0000 1101 OR 1001 1010 1000 0101 0001 1011 1010 0011 There is logic to it and Rd, Rs, Rt Rd <-- Rs • Rt or Rd, Rs, Rt Rd <-- Rs Ú Rt Note: Bit numberingstarts at zero. AND, OR are bitwise logic operations 1011 1011 1111 0111 1011 1111 1010 1111 Example: Set bit 7 of $s9 to ‘1’ (Don’t mess with the other 31 bits) ori $s9, $s9, 0x0080 0x0080 = 0000 0000 1000 0000 Example: Clear bit 14 of $t3 to ‘0’ andi $t3, $t3, 0xBFFF 0xBFFF = 1011 1111 1111 1111

  3. 0010 0011 0111 0110 1010 1111 0000 1101 $t2 0100 0110 1110 1101 0101 1110 0001 101 $s3 Opcode RS RT RD ShAmt Function Shifty Instructions Shift instructions scoot all the bits in a register over sll $s3, $t2, 1 # $s3 <-- $t2 shifted left 1 bit Old MSB: Bit-bucketed 0 0 New LSB: Zero R-Type Instruction srl $t3, $s4, 5 # $t3 <-- $s4 right shifted 5 bits

  4. 0010 0011 0111 0110 1010 1111 0000 1101 $t1 0000 0000 0010 0011 0111 0110 1010 1111 $t1 $t1 0000 0000 0000 0000 0000 0000 1010 1111 0000 0000 0000 0000 0000 0000 0000 0101 $t3 0000 0000 0000 0000 0000 0000 0010 1000 $t3 To access only part of a word, we need the bits on the RHS Using Shifts 1. You need only the 2nd byte of a 4-byte word 8 srl $t1, $t1, 8 Must isolate only the 8 bits on RHS 0000 0000 0000 00000000 0000 1111 1111 Note - extended with 16 0’s andi $t1, $t1, 0x00FF 2. You want to multiply $t3 by 8 (note: 8 equals 23) (equals 5) sll $t3, $t3, 3 # move 3 places to the left (equals 40)

  5. Arithmetic and Logic Unit • The ALU is at the heart of the CPU • Does math and logic • The ALU is primarily involved in R-type instructions • Perform an operation on two registers and produce a result • Where is the operation specified? • The instruction type specifies the operation • The ALU will have to be controlled by the instruction opcode

  6. 0 1 Constructing an ALU - Logic Operations Start out by supporting AND and OR operations Operation 2-to-1 Mux A AB Result A+B B If Operation = 0, Result = A • BIf Operation = 1, Result = A Ú B Two operands, two results.We need only one result... The Operation input comes from logic that looks at the opcode

  7. Ai Bi Sum CarryOut 0 0 0 0 Sum + 0 1 1 0 1 0 1 0 1 1 0 1 CarryOut Sum = Ai BiÚ Ai Bi = Ai ÅBi A i Sum A i B i B i CarryOut A half adder adds two bits, A and Band produces a Sum and CarryOut Half Adder CarryOut = Ai Bi Problem: We often need to add two bits and a CarryIn...

  8. CarryIn A1 Sum + B1 CarryOut Sum Cout A A AB AB 00 01 11 10 00 01 11 10 Cin Cin 0 0 1 1 B B A full adder adds two bits, A and B, and a CarryIn and produces a Sum and CarryOut Full Adder A B CinCoutSum 0 0 0 00 0 0 1 01 0 1 0 01 0 1 1 10 1 0 0 01 1 0 1 10 1 1 0 10 1 1 1 11 0 1 0 1 0 0 1 0 1 0 1 0 0 1 1 1 ÚBCin ÚACin Sum =A Å B Å Cin Cout = AB

  9. Operation A 0 0 Result 1 1 Cin Op (2 bits) + 2 B Cin A Result ALU B Cout Cout Adding to our ALU (Op is now 2 bits) CarryIn Operation Function 00 A • B 01 A Ú B 10 A + B Add an Adder CarryOut Connect CarryIn (from previous bit) and CarryOut (to next bit) Expand Mux to 3-to-1 (Op is now 2 bits)

  10. Cin A0 Result0 ALU0 B0 Cout Cin A1 Result1 ALU1 B1 Cout Cin A2 Result2 ALU2 B2 Cout Cin A31 Result31 ALU31 B31 Cout Putting it all together Cin Operation • Stack 32 of our 1-bit ALU’s together • Each one gets one bit from A and one from B • Connect to common Operation controls • Now we can do 32-bit AND and OR operations • Connect Cout’s to Cin’s • Now, 32-bit adds will work • Note: Carry will ripple through the stages, one at a time • Ripple-Carry Adder Cout

  11. Operation CarryIn • Our ALU can add now, but what about subtraction? • To compute A - B, we can instead compute A + (-B) • In 2’s complement, -B = B + 1 A 0 1 Result 0 + 2 • Add an inverter, and a signal BInvert to get B 1 CarryOut Subtracting Set to 1 for LSB BInvert B B • Now, how about that +1? • CarryIn to LSB is unused (always zero) • Set it to 1! • Subtraction just sets BInvert and Cin to 1 For subtraction: Set CarryInof LSB to 1, Set BInvert to 1

  12. Operation BInvert CarryIn A 0 0 1 1 Result B 0 + 2 2 1 3 CarryOut Support for SLT • We need to support the SLT operation • Set Result to 0000 0000 0000 0000 0000 0000 0000 0001if A <B • A<B is equivalent to(A - B) < 0 • Subtract B from A • If the result is negative, then set LSB of Result to ‘1’, all others to ‘0’ • The result is negative if the MSB after the subtraction is ‘1’ (Two’s complement) Less Less will be ‘0’ for bits 1-31, special for bit 0 We’re going to have to do something differentfor the MSB and the LSB

  13. Operation BInvert CarryIn A 0 1 Result B 0 + 2 1 Less 3 MSB Only CarryOut That tricky MSB • To properly execute the SLT, we need to Set the LSB if the MSB is ‘1’ • (After a subtraction) • Can’t use the ‘Result’ of the MSB • Op will set the Mux to the ‘Less’ Field • Bring out the adder output directly: ‘Set’ Set • Also, we need to check for overflow • Overflow if Cin to MSB is different from Cout of MSB OverFlow

  14. A0 Cin B0 Result0 ALU0 Less Cout A1 Cin B1 Result1 ALU1 0 Less Cout A2 Cin B2 Result2 ALU2 0 Less Cout A31 Result31 Cin B31 ALU31 0 Less Cout The Whole Thing BInvert Cin Operation • Our new and improved 32-bit ALU • Add the BInvert control to each bit • Connect ‘0’ to all the Less inputs except LSB • Connect ‘Set’ output of MSB to ‘Less’ Input of LSB • Set the LSB during SLT when negative • Output OverFlow from MSB OverFlow Set Cout

  15. BInvert Cin Operation A0 Result0 Cin B0 ALU0 Less Cout A1 Result1 Cin B1 ALU1 0 Less Cout Operation A2 Cin B2 ALU2 A Result2 0 Less Cout Zero Result OverFlow Result31 B A31 Cin B31 OverFlow ALU31 Cout 0 Less Set Cout Cout One LastChange We need to add a checkto see if the result is zero Zero

  16. Operation BInvert CarryIn A 0 1 Result 0 B + 2 1 3 Less CarryOut ALU Functions Function BInv Op Carryin Result And 0 00 0 R = A • B Or 0 01 0 R = A Ú B Add 0 10 0 R = A + B Subtract 1 10 1 R = A - B SLT 1 11 1 R = 1 if A < B 0 if A ³ B Since Binvert and Carryin are always the same, we can combine them in to a single signal subtract Note: Adding would be a lot faster if we didn’t use a ripple-carry adder... We also have zero-detect for BEQ,BNE (use subtract). Skipping over Shift operations...

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