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RIFLE : a R esearch I nstrument for FL ash E valuation

RIFLE : a R esearch I nstrument for FL ash E valuation. A ctive T echnologies. Presentation. This file contains a RIFLE instrument presentation A RIFLE’s user demo is shown in the Rifle demo file This demo has been designed for Office 2002, but it may run quite well under Office 2000.

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RIFLE : a R esearch I nstrument for FL ash E valuation

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  1. RIFLE: aResearchInstrumentforFLashEvaluation Active Technologies

  2. Presentation This file contains a RIFLE instrument presentation A RIFLE’s user demo is shown in the Rifle demo file This demo has been designed for Office 2002, but it may run quite well under Office 2000 Active Technologies - RIFLE presentation - October 2003

  3. Index Select the section to visit by clicking on the section name Introduction( 1 min. 15”) Hardware features( 7 min. 10”) System performances( 1 min. 55”) Software architecture( 2 min. 10”) Scientific references( 1 min. 10”) Role of Active Technologies and N-plus-T( 20”) End of presentation Active Technologies - RIFLE presentation - October 2003

  4. Project history 1996 – Kick-off of the RIFLE project, at the Università di Ferrara, Italy 1998 – First prototype: beginning of research activity 2001 – First industrialized release 2002 – Second industrialized release 2003 – Creation of the Academic spin-off Active Technologies for RIFLE commercialization and support Active Technologies - RIFLE presentation - October 2003

  5. Aims of the project Development of a “flexible” instrument for research/characterization activities ATE-like hardware performances Standard software support (C, C++ languages and LabVIEW) Ultra-friendly use Active Technologies - RIFLE presentation - October 2003

  6. Flexible instrument: why New products development and characterization require high flexibility (data acquisition, signal waveforms, voltages, …) “What if” philosophy Possibility of identify and track selected cells Possibility of evaluating the impact of any modification on long-term reliability Possibility of immediate availability of measure’s results Active Technologies - RIFLE presentation - October 2003

  7. End of Section Make your choice by using the PC mouse Index page End of presentation Active Technologies - RIFLE presentation - October 2003

  8. Instrument architecture Active Technologies - RIFLE presentation - October 2003

  9. Features P.C.I. BUS • Standard Bus • DUT (Device Under Test) is treated as an extension of the PC memory: it is simply accessed like an array structure during read/write cycles • PC’s storing and computational capabilities are fully exploited • Storing and computational capabilities can be upgraded by upgrading the PC • Address space: 512Mbytes • Bus width: 8, 16, 32 bits • Bus speed: up to 33 MHz Active Technologies - RIFLE presentation - October 2003

  10. Timing Generator A Programmable state machine translates the PCI cycles into the DUT cycles to match its timing requirements Active Technologies - RIFLE presentation - October 2003

  11. Waveform generators RIFLE can be equipped with up to 16 arbitrary waveform generators. The impact on device performance and long term reliability of any shape and duration modification in the waveform applied during writing operations can be easily evaluated Unused slots for waveform generators can be used to plug-in customized cards to add new hardware features Active Technologies - RIFLE presentation - October 2003

  12. DAC Top Bottom Control Block Waveform generators The generator architecture is based on a high speed 32ksample (or 128ksample) SRAM, managed as a FIFO, where the waveform samples are stored during the measurement setup Active Technologies - RIFLE presentation - October 2003

  13. DAC Top Bottom Control Block Waveform generators When the waveform is generated, its samples are popped from the FIFO memory and converted into an analog signal by a high speed (125 Msps) D/A converter and a current feedback output buffer (140Mhz Bandwidth, 2500 V/s Slew-Rate) Active Technologies - RIFLE presentation - October 2003

  14. DAC Top Bottom Control Block Waveform generators • Output buffer performances: • Output voltage range: up to ± 13 V (trimmerable) • Maximum output current: ± 50 mA • Bandwidth: 140 MHz • Slew rate: 2500 V/s • Different requirements can be obtained by substituting the output buffer or by plugging a specific generator into the motherboard Active Technologies - RIFLE presentation - October 2003

  15. DAC Top Bottom Control Block Waveform generators Single pulse or periodic arbitrary waveforms can be generated The sampling rate is programmable: - The maximum time resolution is 10 ns (@100Mhz) with a maximum pulse duration of 327.68 s (with a 32K sample FIFO) - The minimum time resolution is 327.68 s with a maximum pulse duration of 10.7 s (with the clock signal divided by 32768) Active Technologies - RIFLE presentation - October 2003

  16. Waveform generator synchronization • RIFLE has advanced synchronization capabilities to keep the timing requirements of the DUT and to synchronize all its data acquisition and generation circuits: • All generators can be simultaneously triggered • All generators can be triggered by external events • Waveforms can be arbitrarily and mutually delayed • 3 specific waveform generators have the alternative function of synchronization generators to generate the trigger events for the analog acquisition circuits or for the other arbitrary waveform generators • Analog signal acquisitions can be synchronized with the applied voltage waveforms Active Technologies - RIFLE presentation - October 2003

  17. General purpose I/O 16 digital outputs and 8 digital inputs are provided to drive the DUT internal logic circuits Active Technologies - RIFLE presentation - October 2003

  18. Level Translators All the digital signal levels are translated into the programmable DUT power supply voltage level to support devices with different power requirements The DUT power supply can be programmed from 5V down to 1.2 V The DUT power supply is provided by a 3Amps programmable voltage generator Active Technologies - RIFLE presentation - October 2003

  19. Current Generator A programmable Current Generator provides the reference current required for read and verify operations Active Technologies - RIFLE presentation - October 2003

  20. Direct Memory Access A circuit called DMA is provided to measure the current characteristics of any cell. Both 2D or 3D characteristic can be evaluated. Active Technologies - RIFLE presentation - October 2003

  21. I Voltage Generator Data Bus A/D I/V Converters Switch Matrix A/D Direct Memory Access By means of a switch matrix two data bus lines are selected and a voltage is applied by means of a voltage generator Active Technologies - RIFLE presentation - October 2003

  22. Direct Memory Access I Voltage Generator Data Bus A/D I/V Converters Switch Matrix A/D The currents supplied on these lines are converted into voltages and then digitized in parallel by two 12 bit ADCs with a 2.5s conversion time Active Technologies - RIFLE presentation - October 2003

  23. I Voltage Generator Data Bus A/D I/V Converters Switch Matrix A/D Direct Memory Access The trigger command can be generated by means of a synchronism generator so that the acquisition can start at any desired and synchronized time Active Technologies - RIFLE presentation - October 2003

  24. Power Zero RIFLE has a circuit called Power Zero that performs synchronized high speed current waveform measurements on any DUT signal Active Technologies - RIFLE presentation - October 2003

  25. control signals Switch Matrix FIFO ADC Video Diff. Amp. Power Zero By means of a switch matrixany DUT signal (power supply included) can be selected and connected to the PW0 unit Active Technologies - RIFLE presentation - October 2003

  26. Pulse Generator Power Zero A pulse generator applies a waveform on the selected device pin control signals Switch Matrix FIFO ADC Video Diff. Amp. Active Technologies - RIFLE presentation - October 2003

  27. Power Zero control signals Switch Matrix Pulse Generator A high speeddifferential Amplifier reads the voltage drop across a sensing resistance due to the current flowing FIFO ADC Video Diff. Amp. Active Technologies - RIFLE presentation - October 2003

  28. control signals Switch Matrix Pulse Generator FIFO ADC Third state Video Diff. Amp. Power Zero Any pin of the DUT can also be connected to an alternative voltage generator Active Technologies - RIFLE presentation - October 2003

  29. Power Zero control signals Switch Matrix Pulse Generator FIFO ADC Video Diff. Amp. The current waveform is then sampled at up to 40Msps by a 10 bit A/D converter Active Technologies - RIFLE presentation - October 2003

  30. Power Zero control signals Switch Matrix Pulse Generator FIFO ADC Video Diff. Amp. The samples are stored in a FIFO memory (4Ksample deep) Active Technologies - RIFLE presentation - October 2003

  31. control signals Switch Matrix Pulse Generator FIFO ADC Video Diff. Amp. Power Zero The current waveform conversion and storing can be triggered by means of a synchronism generator so that the waveform acquisition can start at any desired time, synchronously with the applied pulse Active Technologies - RIFLE presentation - October 2003

  32. Calibration The hardware calibration is made during the first factory system testing and doesn’t need any user intervention. A further software fine calibration can be periodically executed by the user. By means of a dedicated calibration board and a multimeter, the user can adjust both the offset and gain errors of all analog circuits following the step by step procedure of the calibration software provided with the calibration board. Active Technologies - RIFLE presentation - October 2003

  33. End of Section Make your choice by using the PC mouse Index page End of presentation Active Technologies - RIFLE presentation - October 2003

  34. Performances Current unit resolutions and full-scales DMA current measurement unit: 2 full-scales: ±500 A,12 bit resolution ±50 A, 12 bitresolution Active Technologies - RIFLE presentation - October 2003

  35. Performances Current unit resolutions and full-scales PW0 current measurement unit: 3 full-scales:  500 A, 10 bit resolution  5 mA, 10 bit resolution 50 mA, 10 bit resolution Active Technologies - RIFLE presentation - October 2003

  36. Performances Current unit resolutions and full-scales Current generator: 2 full-scales:  600 A, 12 bit resolution  60 A, 12 bit resolution Active Technologies - RIFLE presentation - October 2003

  37. Performances Time requirements (examples) The time requirements for standard operations strongly depend on device speed and bandwidth Time limitations are usually imposed by the device itself The following time requirements refer to a 8.6 Mbit sector of a commercial device Active Technologies - RIFLE presentation - October 2003

  38. Performances Time requirements (examples) Minimum read cycle (@32 bit bus width, 0 wait-states): 4 clock periods  200 ns (@20Mhz) Active Technologies - RIFLE presentation - October 2003

  39. Performances Time requirements (examples) Programming: 1 sector (8.6 Mcells), with verify, 1 single pulse applied to each cell, 8bit parallelism: 1.9 s Active Technologies - RIFLE presentation - October 2003

  40. Performances Time requirements (examples) Erasing: 8.6 Mcells sector, with verify, 1 pulse applied: 1.20 s Active Technologies - RIFLE presentation - October 2003

  41. Performances Time requirements (examples) Threshold Voltage Distributions with 20 resolution levels: 18 s Active Technologies - RIFLE presentation - October 2003

  42. Performances Time requirements (examples) Threshold Voltage Maps with 20 resolution levels: 1’ 29 s Active Technologies - RIFLE presentation - October 2003

  43. Performances Time requirements (examples) Criterion based subset identification: identification of 1000 cells complying with a particular requirement (i.e., the lowest, the highest, etc.): 40.1 s Active Technologies - RIFLE presentation - October 2003

  44. Performances Time requirements (examples) Vth tracking for subset of cells: threshold voltage measure of the identified 1000 cells : 5.4 s Active Technologies - RIFLE presentation - October 2003

  45. End of Section Make your choice by using the PC mouse Index page End of presentation Active Technologies - RIFLE presentation - October 2003

  46. Software Architecture The instrument software is hierarchically organized to hide the implementation details and, by means of different programming languages, to create a powerful and easy to use environment RIFLE instrument Active Technologies - RIFLE presentation - October 2003

  47. System Level Interface: Virtual Device Driver Software Instrument Driver At the lowest level, just above the hardware, there is the instrument driver. It belongs to the PC Operating System and it must not bemodified by the user. It’s written in “C” and assembler languages. RIFLE instrument Active Technologies - RIFLE presentation - October 2003

  48. Application Program Interface: Dynamic Link Libraries Software API At a higher layer we find the API. It’s a libraryoffunctions that work as an interface between the driver routines and the higher level programming languages. Also this layer must not be modified by the user. System Level Interface: Virtual Device Driver RIFLE instrument Active Technologies - RIFLE presentation - October 2003

  49. Chip Dependent Interface: Dynamic Link Libraries Software Chip Dependent Interface This is the first layer that can be modified by the user. It consists of a library of functions specific for the DUT. It’s written in “C” or “C++” to achieve high efficiency and must be implemented for any new device. Application Program Interface: Dynamic Link Libraries System Level Interface: Virtual Device Driver RIFLE instrument Active Technologies - RIFLE presentation - October 2003

  50. High Level Program Interface: LabVIEW Virtual Instrument Libraries Chip Dependent Interface: Dynamic Link Libraries Application Program Interface: Dynamic Link Libraries System Level Interface: Virtual Device Driver RIFLE instrument Software High level Program Interface The High Level Program Interface is written in the “G” languageof the National Instrument LabVIEW program. At this level, by means of several panels, the user can control any instrument operation, execute measurements and graphically analyze data. Active Technologies - RIFLE presentation - October 2003

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