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Designing Static CMOS Logic Circuits

Designing Static CMOS Logic Circuits. At every point in time (except during the switching. transients) each gate output is connected to either. V. or. V. via a low-resistive path. DD. ss. The outputs of the gates assume at all times the value.

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Designing Static CMOS Logic Circuits

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  1. Designing Static CMOSLogic Circuits

  2. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). Static CMOS Circuits

  3. Static Complementary CMOS VDD In1 PMOS only In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN PUN and PDN are logically dual logic networks

  4. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high

  5. PMOS Transistors in Series/Parallel Connection

  6. CL CL CL CL Threshold Drops VDD VDD PUN S D VDD D S 0  VDD 0  VDD - VTn VGS PDN VDD 0 VDD |VTp| VGS D S VDD S D

  7. Complementary CMOS Logic Style

  8. Example Gate: NAND

  9. Example Gate: NOR

  10. B A C D Complex CMOS Gate OUT = D + A • (B + C) A D B C

  11. Constructing a Complex Gate • Logic Dual need not be Series/Parallel Dual • In general, many logical dual exist, need to choose one with best characteristics • Use Karnaugh-Map to find good duals • Goal: find 0-cover and 1-cover with best parasitic or layout properties • Maximize connections to power/ground • Place critical transistors closest to output node (a) pull-down network SN1 SN4 D SN3 SN2 F F A D B D (c) complete gate C C F B A B C (b) Deriving the pull-up network hierarchically by identifying sub-nets D A A B C V V DD DD

  12. Example: Carry Gate • F = (ab+bc+ac)’ • Carry ‘c’ is critical • Factor c out: • F=(ab+c(a+b))’ • 0-cover is n-pd • 1-cover is p-pu

  13. Example: Carry Gate (2) • Pull Down is easy • Order by maximizing connections to ground and critical transistors • For pull up – Might guess series dual– would guess wrong

  14. Example: Carry Gate (3) • Series/Parallel Dual • 3-series transistors • 2 connections to Vdd • 7 floating capacitors

  15. Example: Carry Gate (4) • Pull Up from 1 cover of Kmap • Get a’b’+a’c’+b’c’ • Factor c’ out • 3 connections to Vdd • 2 series transistors • Co-Euler path layout • Moral: Use Kmap!

  16. Cell Design • Standard Cells • General purpose logic • Can be synthesized • Same height, varying width • Datapath Cells • For regular, structured designs (arithmetic) • Includes some wiring in the cell • Fixed height and width

  17. Standard Cell Layout Methodology – 1980s Routing channel VDD signals GND

  18. Standard Cell Layout Methodology – 1990s Mirrored Cell No Routing channels VDD VDD M2 M3 GND Mirrored Cell GND

  19. V DD Standard Cells N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” Out In 2 Rails ~10 GND Cell boundary

  20. V V DD DD Standard Cells With minimaldiffusionrouting With silicided diffusion Out In Out In GND GND

  21. V DD Standard Cells 2-input NAND gate A B Out GND

  22. V V DD DD Stick Diagrams Contains no dimensions Represents relative positions of transistors Inverter NAND2 Out Out In A B GND GND

  23. X PUN C i VDD X B A j PDN GND Stick Diagrams Logic Graph A j C B X = C • (A + B) C i A B A B C

  24. Two Versions of C • (A + B) A C B A B C VDD VDD X X GND GND

  25. Consistent Euler Path X C i VDD X B A j A B C GND

  26. OAI22 Logic Graph X PUN A C D C B D VDD X X = (A+B)•(C+D) C D B A A B PDN A GND B C D

  27. Example: x = ab+cd

  28. Properties of Complementary CMOS Gates Snapshot High noise margins : V and V are at V and GND , respectively. OH OL DD No static power consumption : There never exists a direct path between V and DD V ( GND ) in steady-state mode . SS Comparable rise and fall times: (under appropriate sizing conditions)

  29. CMOS Properties • Full rail-to-rail swing; high noise margins • Logic levels not dependent upon the relative device sizes; ratioless • Always a path to Vdd or Gnd in steady state; low output impedance • Extremely high input resistance; nearly zero steady-state input current • No direct path steady state between power and ground; no static power dissipation • Propagation delay function of load capacitance and resistance of transistors

  30. Rp Rp Rp Rp Rp Rp A A A B B A Cint Rn CL CL CL Rn Rn Rn Rn B A B A A Cint Switch Delay Model Req A A NOR2 INV NAND2

  31. Rp Rp B A Cint CL Rn A Input Pattern Effects on Delay • Delay is dependent on the pattern of inputs • Low to high transition • both inputs go low • delay is 0.69 Rp/2 CL • one input goes low • delay is 0.69 Rp CL • High to low transition • both inputs go high • delay is 0.69 2Rn CL Rn B

  32. Delay Dependence on Input Patterns A=B=10 A=1 0, B=1 A=1, B=10 Voltage [V] time [ps] NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF

  33. Rp Rp 2 2 Rp Rp B A B A Rn Cint Cint CL CL Rn Rn Rn B A B A 1 1 Transistor Sizing 4 4 2 2

  34. Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance

  35. A D Transistor Sizing a Complex CMOS Gate B 8 6 4 3 C 8 6 4 6 OUT = D + A • (B + C) A 2 D 1 B 2 C 2

  36. D C B A C3 C2 C1 CL Fan-In Considerations A Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. B C D

  37. quadratic tpHL tp linear tp as a Function of Fan-In Gates with a fan-in greater than 4 should be avoided. tp (psec) tpLH fan-in

  38. tp as a Function of Fan-Out All gates have the same drive current. tpNOR2 tpNAND2 tpINV tp (psec) Slope is a function of “driving strength” eff. fan-out

  39. tp as a Function of Fan-In and Fan-Out • Fan-in: quadratic due to increasing resistance and capacitance • Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO

  40. Practical Optimization • The previous arguments regarding tp raise the question – why build nor at all? • Criticality is not a path– but a transition so it is usually only on rising or falling (but not both) • NOR forms have bad pull-up but good pull down • NAND forms have bad pull-down but good pull up • Determine the critical transition(s) and design for them– using Elmore or Simulation on the appropriate edge only! • Logical Effort presupposes uniform rise and fall times, so good in general, but can be beat • Static Timing Analyzers nearly always get this wrong!

  41. C3 C2 C1 CL Fast Complex Gates:Design Technique 1 • Transistor sizing • as long as fan-out capacitance dominates • Progressive sizing Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) InN MN In3 M3 In2 M2 Can reduce delay by more than 20%; decreasing gains as technology shrinks In1 M1

  42. C2 C1 C1 C2 CL CL Fast Complex Gates:Design Technique 2 • Transistor ordering critical path critical path 01 charged charged 1 In1 In3 M3 M3 1 1 In2 In2 M2 discharged M2 charged 1 In3 discharged In1 charged M1 M1 01 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL

  43. Fast Complex Gates:Design Technique 3 • Alternative logic structures F = ABCDEFGH

  44. CL CL Fast Complex Gates:Design Technique 4 • Isolating fan-in from fan-out using buffer insertion

  45. Fast Complex Gates:Design Technique 5 • Reducing the voltage swing • linear reduction in delay • also reduces power consumption • But the following gate may be much slower! • Large fan-in/fan-out requires use of “sense amplifiers” to restore the signal (memory) tpHL= 0.69 (3/4 (CL VDD)/ IDSATn ) = 0.69 (3/4 (CL Vswing)/ IDSATn )

  46. Sizing Logic Paths for Speed • Frequently, input capacitance of a logic path is constrained • Logic also has to drive some capacitance • Example: ALU load in an Intel’s microprocessor is 0.5pF • How do we size the ALU datapath to achieve maximum speed? • We have already solved this for the inverter chain – can we generalize it for any type of logic?

  47. Buffer Example In Out CL 1 2 N (in units of tinv) For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci ~ 4 How to generalize this to any logic path?

  48. Logical Effort p – intrinsic delay (3kRunitCunitg) - gate parameter  f(W) g – logical effort (kRunitCunit) – gate parameter  f(W) f – effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide everything by tinv (everything is measured in unit delays tinv) Assume g = 1.

  49. Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = Cout/Cin Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

  50. Logical Effort • Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates • Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current • Logical effort increases with the gate complexity

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