CSC: 345 Computer Architecture

1. CSC: 345 Computer Architecture Jane Huang Lecture 9 Micro-operationsComputer Arithmetic

2. Defining the function of the processor • Operations • Addressing modes • Registers • I/O module interfaces • Memory module interface • Interrupt processing structure Defined by the instruction set. Defined by setting the system bus. Defined partially by the bus, and partially by the support offered by the processor to the OS.

3. The primitive components of an instruction • A program consists of a sequence of instruction cycles. • Each instruction cycle is made up of a number of smaller units.(fetch, indirect, execute, interrupt etc). • A further decomposition into micro-operations is possible. Micro-ops are the atomic operations of the processor.

4. The Fetch Cycle The fetch cycle – fetches an instruction at the start of the instruction cycle. The organization involves four registers: • Memory Address Register (MAR)Connected to the address lines of the system bus. Hold address to be read or written from/to memory. • Memory Buffer Register (MBR)Connected to the data lines of the system bus. Holds data to be read or written from/to memory. • Program Counter (PC)Holds address of next instruction to be fetched. • Instruction Register (IR)Holds last instruction fetched.

5. 0001000000100000 0000000001100101 A dynamic example of the fetch cycle. MAR 0000000001100100 MBR PC 0000000001100100 0. At the start of the fetch cycle the address of the next instruction is in the PC.. IR 0001000000100000 1. Address is moved from PC to MAR. AC • Bring in the instruction: MAR placed on address bus, control unit issues a READ command, the result appears on the data bus, and is placed into the MBR. • 3. PC is incremented. (These two actions do not interfere with each other and can therefore occur at the same time). t1: MAR  (PC) t2: MBR  Memory PC  PC + 1 t3: IR  (MBR) 4. Contents of MBR moved to IR (freeing up MBR for use during an indirect cycle).

6. Sequence of Micro-operations t1: MAR  (PC) t2: MBR  Memory PC  PC + 1 t3: IR  (MBR) • A clock must be available for timing purposes and emit regularly spaced clock pulses. • Each micro-operation must be performed within a single time unit. • Groupings of micro-ops must follow two simple rules: • Proper sequence of events must be followed.MAR  PC must precede MBR  Memory • Conflicts must be avoided that may results in unpredictable results.MBR  Memory and IR  MBR should not occur in the same time unit. • Incrementing the PC involves an addition. To minimize circuitry – this may be performed by the ALU.

7. The Indirect Cycle Assuming a one-address instruction format supporting both direct and indirect addressing. If an indirect address is used – an indirect cycle must precede the execute cycle. Address field of IR transferred to MAR, and used to fetch effective address (EA) of the operand. This EA is placed into the correct field of the IR. (The IR now appears as if an indirect cycle were not being used).(?? Problems) t1: MAR  (IR(Address)) t2: MBR  Memory t3: IR(Address) (MBR(Address))

8. The Interrupt Cycle • The interrupt cycle varies from • processor to processor. • A very simple example would • involve: • Transfer contents of PC to MBR. • Load MAR with address at which PC should be saved. • Update the PC with the address of the interrupt routine. • Save the original PC contents to memory. t1: MBR  (PC) t2: MAR  Save_Address PC  Routine_Addresst3: Memory  (MBR)

9. The Execute Cycle • The execute cycle is not so predictable. • For a machine with N different opcodes there are N different sequences of micro-operations. • For example: Add Instruction ADD R1, X t1: MAR  (IR(Address)) t2: MBR  Memory t3: R1  (R1) + (MBR) Increment and skip if zero ISZ X t1: MAR  (IR(Address)) t2: MBR  Memory t3: MBR  (MBR) + 1 t4: Memory  (MBR) if ((MBR) = 0) then (PC  (PC) + 1)

10. Tying sequences of micro-operations together. • For four stages we can use a 2 bit register - Instruction cycle code (ICC) to represent the current state of the processor where: • 00 = Fetch 01 = Indirect 10 = Execute 11 = Interrupt 11 (Interrupt) ICC? 00 (Fetch) 10 (Execute) 01 (Indirect) Setup Interrupt ReadAddress Fetch instruction Opcode? ICC = 00 Interrupt? ICC = 10 Indirectaddress? ICC = 11 ICC = 00 ICC = 10 ICC = 01

11. Basic functional units of the processor are: • ALUProvides functionality • RegistersStore data internal to the processor • Internal data pathsMove data between registers and between registers & ALU • External data pathsLink registers to memory and I/O modules (usually via a system bus) • Control UnitControls the execution of operations within the processor through • Sequencing a series of micro-operations. • Executing each micro-operation. • Control unit accomplishes this through the use of control signals.

12. Instruction registeropcode determines which micro-ops to execute. Control signals within CPU Flagsto determine statusof processor and outcome of previousALU ops. Control signals from system bus Clockto ‘keep time’ Control signals to system bus Control Signals Control unit needs: • Inputs to sense the state of the system • Outputs to control the behavior of the system • Internal logic to perform sequencing and execution. Control Unit

13. t1: MAR  (PC) t2: MBR  Memory PC  PC + 1 t3: IR  (MBR) • Control Signals • Three types of control signals: • To activate an ALU function • To activate a data path • External signals on system bus or other external interface. • Signals are applied as binary inputs to individual logic gates. • Fetch Cycle • 1st step is to transfer contents of PC to MAR.Control unit activates the control signals that open the gates between the bits of the PC and the bits of the MAR. • 2nd step is to read a word from memory into the MBR and increment the PC. • Control signal to open gates allowing contents of MAR onto the address bus. • Memory read control signal on the control bus. • Control signal that opens gates allowing the contents of the data bus to be stored in the MBR • Control signals to logic that add 1 to PC and store results back to PC.

14. Control Units • Hardwired implementationCombinatorial circuit.Inputs are logic signalsOutputs logic signals – acting as control signals. • Microprogrammed implementationAvoids complexities of hardwired implementation.Requires fast and relatively inexpensive control memory.

15. Hardwired implementation • Control unit takes the opcode from the instruction register. • A decoder is used to generate a unique signal for each opcode. • Each of the 2n different input patterns will activate a unique output. Instruction Register Decoder Timinggenerator Control Unit Clock Flags Control Signals

16. Control Unit Logic • For each control signal we need to derive a Boolean expression as a function of inputs. • Consider C5 as an example.

17. Control Unit Logic • We can define two new input symbols P and Q such that: • PQ = 00 Fetch CyclePQ = 01 Indirect CyclePQ = 10 Execute CyclePQ = 11 Interrupt Cycle • C5 can then be defined as P` • Q` • T2 + P` • Q • T2 in order to assert the control signal C5 during the second time unit of both the fetch and indirect cycles. • However – C5 is also needed during the execute cycle. If we assume that only 3 instructions read from memory (LDA, ADD, and AND) then we could add these into the boolean expression.

18. Computer Arithmetic • Twos Complement Addition • An overflow condition occurs if two numbers are the same sign, and the result is of the opposite sign. • 5 + 4 •  0101 •  0100 • 0101 • + 01001001 (overflow condition)

19. Multiplication • Some general observations • Multiplication involves the generation of partial products – one for each digit in the multiplier. • Partial products are summed to produce the final product. • Partial products are very simple to define for binary multiplication. If the digit is a ‘one’ the partial product is the multicand, otherwise the partial product is zero. • The total product is the sum of the partial products. Each successive partial product is shifted one position to the left. • The multiplication of two n-bit binary numbers results in a product of up to 2n bits in length. 1011 X 1101 1011 0000 1011 1011 10001111

20. Simplifying Multiplication • The processor can keep a running product rather than summing at the end. • For each ‘1’ in the multiplier we can apply an add and a shift. • For each ‘0’ only a shift is needed. • ( Binary addition truth tables and circuit)

21. Multiplier and multiplicand are loaded into registers Q and M. • A third register (A) is initially set to zero. • A one-bit C register (initialized to zero) holds carry bits.

22. Group Exercise:Group 1: 3 X 7, Group 2: -3 X 7, Group 3: 3 X -7, Group 4: -3 X -7

23. Observation M X (00011110) = M X (24 + 23 +22 + 21) = M X (16 + 8 + 4 + 2) = M X 30 The number of operations can be reduced to two if we observe that: 2n + 2n-1 + …. + 2n-k = 2n+1 – 2n-k M X (00011110) = M X (25 - 21) = M X (32 - 2) = M X 30

24. Booth’s Algorithm • Multiplier and multiplicand are placed in Q and M registers. • A 1-bit register is placed to the right of the least significant bit (Q0) and designated Q-1. • Control logic scans the bits of the multiplier one at a time – but a bit AND its bit to the right are examined. If the bits are the same (1-1 or 0-0) then all bits of the A,Q, and Q-1 registers are shifted to the right 1 bit. If the two bits differ, then the multiplicand is added depending on whether the bits are 0-1 or 1-0. Addition is followed by a right arithmetic shift.