Clock Board Test and Preliminary Acceptance Criteria Ciemat (Madrid), April 2009

1. Clock Board Test • and • Preliminary Acceptance Criteria • Ciemat (Madrid), April 2009 • Juan de Vicente, Javier Castilla, Gustavo Martínez

2. Introduction • CB configuration • Jumper settings and power checking • FPGA configuration CB test • General checks • Revision of CBv1 testing (performed by hand) • Improvements for CBv2 testing • automation of some repetitive task • adoption of a measureable acceptance criteria for CB production • Checkout documentation • Future upgrade for Clock Transition Board testing

3. CB configuration CB configuration (Jumpers settings) TOP view Rst aux. JP9 JP1 Prog. FPGA CLK ref. 1 JP10 1 JP2 Prog. FPGA Gnd JP11 1 JP3 Prog. FPGA CLK ref. JP12 1 1 JP4 Config. Clk aux Gnd JP13 1 JP5 CLK ref. Gnd JP15 1 JP6 Supply 3.3v Gnd JP17 1 JP7 Gnd Gnd JP19 Gnd JP8 Gnd JP9

4. Power supply checking Analog Voltages Digital Voltages TP41 GND reference TP42 GND reference TP35 +VAC +15v TP44 +5VIN +5v TP36 -VAC -15v TP43 +3.3VIN -3.3v TP38 +5VA +5v TP39 -5VA -5v

5. CB configuration FPGA configuration • Firmware • Load files DocDb#2420 • Source files DocDb#2299

6. CB test • General checks: • Clock channel chain (126 electronic chains) • Telemetry • Clock waveform • Front panel ports

7. 1. Clock channel chain checking • Goals • Ensure the range ±10 volts for all clock channels (126) • Detecting possible defective components, assembly faults, etc. • Produce the calibration file • To provide an acceptance criteria • Method • Calibration • To calculate calibration constants (coef1,coef2) for all clocks • Visual inspection of the calibration file for prematurely anomalies detection • Updating csv file with the calibration file • Clock Channel histogram test • Histogramming the differences between programmed voltages and measured voltages • Computing rms

8. 1. Clock channel chain checking CBv1 calibration review By hand procedure for each Clock DAC loop MEC by hand connection clock-multimeter by hand setting ±10 volts in DAC counts with MEC by hand readout of the multimeter Computing calibration constants from data panDaemon Parallel port Socket Serial port Systran Multimeter 1 Clock CBv1

9. 1. Clock channel chain checking CBv1 calibration review By hand procedure for each Clock DAC loop MEC by hand connection clock-multimeter by hand setting ±10 volts in DAC counts with MEC by hand readout of the multimeter Computing calibration constants from data Drawbacks of by hand process - 128 measurements by hand - Error prone panDaemon Parallel port Socket Serial port Systran Multimeter 1 Clock CBv1

10. Out port (meter) 135 clocks Input Connector 9 CCD emulator 1 clock Mux Out port (scope) Improving Clock Board Testing Setup for CBv2 TDS5000 Scope 5 Clock output Monsoon crate 2 3 Clock Board V1/V2 9CCD Emulator + Mux 135:1 CTB V 1.1 MCB Video 160-pin cable Systran Link Clock output PAN PC Parallel Port 1 4 Multimeter/Scope THS710 Serial Port 2 1 3 5 4

11. 1. Clock channel chain checking for each Clock DAC loop selectClockFromParallelPort setClock(±10 volts in DAC counts) readoutClockVoltageFromSerialPort output: CBcalibration.csv Automatic CB calibration Multimeter THS730 CBcalibration.exe MEC 1 Clock panDaemon Parallel port Serial port Socket Socket Serial port Mux Parallel port Systran Clock cable (135) CCD emulator BOARD CBv2

12. 1. Clock channel chain checking calibration file inspection visual inspection of calibration file to detecting anomalous values Anomalous value due to defective components

13. 1. Clock channel chain checking Clock Channel histogram test • Goals • Once calibrated • Histogramming the differences between programmed voltages and measured voltages • Procedure • Measuring 9 points (±8,±6,±4,±2,0 volts) per clock DAC • 2 DAC per clock, 126 clocks -> 2268 DAC clock voltage measurements (9x2x126) • Computing rms • Constraints • DAC resolution= 95 mV(+10 to -10 volts within operational DAC range: 22 to 233 DAC counts) • Multimeter resolution=10 mV • Electronic tolerances

14. 1. Clock channel chain checking Clock channel histogram test Multimeter THS730 CBhistogram.exe MEC 1 Clock for each Clock DAC loop panDaemon Parallel port Serial port selectClockfromEmuBoard( ) Socket Socket setClock(±8, ±6, ±4,±2,0 volts ) Serial port measureClockVoltage( ) Mux Parallel port output: CBhistogram.csv Systran Clock cable (135) CCD emulator BOARD CBv2

15. 1. Clock channel chain checking Clock channel histogram test • Result • Histogram of differences between programmed voltages and measured voltages • Computing the rms of the differences (rms_clocks) rms_clocks=73mV rms_clocks=258mV ok Bad channel

16. 1. Clock channel chain checking Acceptance criteria: Clock Channel rms (rms_clocks) • rms_clocks<150mV rms_clocks=73mV

17. 2. Telemetry channel checking • Goals • Detecting possible defective components in telemetry channels • Computing rms • Method • Histogram • Measuring 9 points (± 8,±6,±4,±2,0) per clock DAC setting • 756 DAC clock voltage measurements (42 clocks x 2 DACs x 9 settings) • Computing rms

18. 2. Telemetry channel checking for each Clock DAC loop setClock(±8, ±6,±4,±2,0 volts ) Socket getClockTel( ) Telemetry channel histogram CBhistogram.exe MEC panDaemon Parallel port Socket Serial port output:CBhistogram_tel.csv Systran CBv2

19. 2. Telemetry channel checking Telemetry channel histogram • Result • Histogram of the differences of programmed voltage and measured voltages in telemetry • rms_tel Rms_tel=360mV Rms_tel=101 mV Bad channel ok

20. 2. Telemetry channel checking Acceptance criteria: Telemetry rms rms_tel<200mV rms=101 mV ok

21. 3. Clock waveform visualization • Procedure • The output of the mux of the CCDemulation board is connected to the scope • Initializing MEC in continuous mode: clocks running periodically • Running exploreSignals program • A flexible program for selecting any clock out of 135 • By order, by name, by CCD, etc. • Visualization of all clock waveforms at the scope

22. Clock waveform visualization MEC CB exploreSignals 2. Waveform visualization scope 1 Clock Initialization Run clocks periodically (Continuos mode) Parallel port loop 1. selectClock( ) Socket Serial port Mux Parallel port Systran Clock cable (135) CCD emulator BOARD CBv2

23. 4. Front panel checking • Procedure • Clocks are programmed with incremental values according to their order in the clock frame. • Then clocks are selected in order in the front panel and verified their values with the multimeter

24. Front panel check MEC CB frontPanel panDaemon Parallel port for each Clock loop Socket setClock(i) to a value Socket Serial port muxSlct(i) Voltage Level visualization scope Systran 1 Clock FrontPanel CBv2

25. Checkout documentation

26. Clock Transition board testing • Next CB testing setup upgrade: • Including the new cable for testing CTBv2 • A verified CTB will be used for testing all CBv2.1 • On the opposite, a verified CB will be used for testing the rest of CTB

27. Conclusion • Setup for testing the Clock Board production almost ready at CIEMAT (Madrid) • Automatic calibration procedure • Automatic clock channels verification • Automatic telemetry verification • Clock waveform verification • Front panel verification • Two measurable acceptance criteria: • clock channel rms • telemetry rms • Checkout documentation • Next upgrade for testing the CTB (requiring the new cable)