Marseille 30 January 2013

1. CLB: Current status and development on CLBv2 in Valencia David Calvo IFIC (CSIC – Universidad de Valencia) Marseille 30 January 2013

2. TDC: DESIGN KC705 LVDS Input Signal Output 48 bits (Resolution: 1ns) RECOVERY UNIT DESERIALIZER FIFO 8 bits 32 bits 8 bits Header Time Stamp Pulse width

3. TDC: 31 CHANNELS Enable Interface KC705 Ch.1 LVDS Input Signal Ch.1 Ch.2 Output (48 bits) MULTIPLEXER PC SIGNAL DISTRIBUTION Ch.31 Ch.31

4. TDC: TEST Enable Interface KC705 ML605 Ch.1 Well-known pattern LVDS Input Signal Ch.1 Ch.2 Output (48 bits) MULTIPLEXER PC SIGNAL DISTRIBUTION Ch.31 Ch.31

5. TDC: PATTERNS TO TEST CHANNEL 1 CHANNEL 2 Jitter = 0.3 ns

6. TDC: PATTERN TO TEST Patternsreplicated250 times 1000 pulses x channel CHANNEL 1 CHANNEL 2

7. TDC: RESULT CHANNEL 1 CHANNEL 2 Pulse width counts counts ns ns

8. TDC: RESULT CHANNEL 2 CHANNEL 1 Time betweenpulses counts counts ns ns

9. LM32 DEVELOPMENTS IN VALENCIA • LM32 SOC with several wishbone slaves (32 bits bus): • BRAM • UART • TIMER • I2C0 Nanobeacon • I2C1 Temperature and Humidity sensor (DIGIPICCO) • GPIO Data Xilinx Spartan-6 Wishbone shared bus (32 bits) Nano Beacon Debug LEDs GPIO TIMER 2nd CPU LM32 UART I2C0 I2C1 BRAM Temp and Humidity Sensor RS-232 HYPERTERMINAL

10. LM32 DEVELOPMENTS IN VALENCIA IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S State Machine Management & Config. Pause Frame Fifo ADC Hydrophone TxPacket Buffer 32KB TxPort 1 TxPort 2 Tx Stream Select Tx_pkt2mac Tx_data2buf Management & Control Flags TxPort_m S S Nano Beacon M M M S M M M M M Debug LEDs WB Crossbar (1x7) WB Crossbar (3x2) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C UART SPI Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS, 125 MHz) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus

11. NEXT STEPS IN VALENCIA (I) IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S State Machine Management & Config. Pause Frame Fifo ADC Hydrophone TxPacket Buffer 32KB TxPort 1 TxPort 2 Tx Stream Select Tx_pkt2mac Tx_data2buf Management & Control Flags TxPort_m S S Nano Beacon M M M S M M M M M Debug LEDs WB Crossbar (1x7) WB Crossbar (3x2) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C UART SPI Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS, 125 MHz) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus

12. NEXT STEPS IN VALENCIA (II) IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S State Machine Management & Config. Pause Frame Fifo ADC Hydrophone TxPacket Buffer 32KB TxPort 1 TxPort 2 Tx Stream Select Tx_pkt2mac Tx_data2buf Management & Control Flags TxPort_m S S Nano Beacon M M M S M M M M M Debug LEDs WB Crossbar (1x7) WB Crossbar (3x2) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C UART SPI Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS, 125 MHz) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus

13. NEXT STEPS IN VALENCIA (III) IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S State Machine Management & Config. Pause Frame Fifo ADC Hydrophone TxPacket Buffer 32KB TxPort 1 TxPort 2 Tx Stream Select Tx_pkt2mac Tx_data2buf Management & Control Flags TxPort_m S S Nano Beacon M M M S M M M M M Debug LEDs WB Crossbar (1x7) WB Crossbar (3x2) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C UART SPI Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS, 125 MHz) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus

14. NEXT STEEPS IN VALENCIA (IV) • Implement reconfigurability: • A.- To use the multiboot capabilities of the KINTEX • B.- To be able to write on the SPI FLASH with the LM32 Data Xilinx Kintex KC705 Wishbone shared bus (32 bits) 2nd CPU LM32 SPI Multiboot image – upgraded image (read /write) Golden Image (read only) SPI QFLASH MEMORY

15. THANKS FOR YOUR ATTENTION!

16. LM32 developments in Valencia IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S State Machine Management & Config. Pause Frame Fifo ADC Hydrophone TxPacket Buffer 32KB TxPort 1 TxPort 2 Tx Stream Select Tx_pkt2mac Tx_data2buf Management & Control Flags TxPort_m S S Nano Beacon M M M S M M M M M Debug LEDs WB Crossbar (1x7) WB Crossbar (3x2) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C UART SPI Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS, 125 MHz) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus