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Front End Process

Front End Process. 2002 ITRS Conference July 24, 2002 San Francisco, CA. Purpose. Review Linkage between FEP Technology Areas and FEP difficult challenges Identify year 2002 updates Identify year 2003 projects and plans. FEP Technology Areas.

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Front End Process

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  1. Front End Process 2002 ITRS Conference July 24, 2002 San Francisco, CA

  2. Purpose • Review Linkage between FEP Technology Areas and FEP difficult challenges • Identify year 2002 updates • Identify year 2003 projects and plans

  3. FEP Technology Areas • Each technology area is managed by a technology working group • Starting Materials • Surface Preparation • Critical Dimension Etch • Thermal/Films (MOSFET Gate Stack) • Doping • Memory • DRAM • FLASH • FeRAM

  4. Starting Materials Year 2002 Updates & Year 2003 Projects

  5. Starting Materials • Working Group Co-Chairs - Howard Huff-Sematech - Dave Myers – TI • Key Near Term Difficult Challenges Linked to Starting Materials • Extension of Oxynitride gate dielectric => crystal and surface defects, surface roughness • Introduction of High-k gate dielectric=> crystal and surface defects, surface roughness • CD Control => site flatness, crystal and surface defects • Statistically significant characterization of surfaces having very low defect counts=> Wafer state characterization, specifications

  6. Starting Materials • Long Term Difficult Challenges linked to Starting Materials • Introduction of Non-Standard Double Gate Devices=> • SOI Substrates • Extension of Planar CMOS => SOI Substrates, Strained Silicon SOI • Second Generation High-K gate dielectric layer=> crystal and surface defects, surface roughness, • CD Control=> crystal and surface defects, surface roughness, site flatness • Starting Materials beyond 300mm=> are current methods of wafer production economically scalable to ~450mm? Are substrate alternatives required?

  7. Starting Materials- 2002 Updates and 2003 Projects • 2002 Updates- • Minor text corrections • Update Cell Keys for supplier capability and metrology readiness • remaining open issue: wafer edge exclusion • 2003 Projects • Update all tables based on new MPU and DRAM chip sizes • Update SOI and add Strained Silicon SOI • Starting Materials beyond 300mm • See posters for details • Anyone interested in participation on 2003 projects see poster for sign-up instructions.

  8. Surface Preparation 2002 Updates and 2003 Projects

  9. Surface Preparation • Working Group Co-Chairs - Jeff Butterbaugh, FSI International - Debbie Riley, AMD • Key Near Term Difficult Challenges Linked to Surface Preparation • Control of surface defects, contamination and roughness associated with new materials and processes • Scaled oxynitride gate stacks • High-k gate stacks • Scaled DRAM storage capacitors • Scaled Flash Memory storage cells • FeRAM • Statistically significant characterization of surfaces having very low defect counts=> Wafer state characterization, specifications

  10. Surface Preparation • Long Term Difficult Challenges linked to Surface Preparation • Control of surface defects, contamination, and roughness associated with new materials and processes • Scaled volatile and non-volatile memory • Second generation high-k gate dielectric • Non-standard, double gate CMOS devices

  11. Surface Preparation- 2002 Updates and 2003 Projects • 2002 Updates- See FEP Posters for greater detail • Updated defect requirements based on change in wafer edge exclusion • Correct table note text errors • 2003 Projects- See FEP Posters for greater detail • With Lithography- backside particle model and requirements • Coordinate with other TWG’s to achieve uniform formats for defect requirement determination and reporting • With Interconnect- coordinate BEOL Surface prep models and requirements • Channel mobility based model for surface roughness • Review drivers for critical metals • Process flow contamination from high-k materials • Interested persons see Posters for 2003 project sign-up instructions.

  12. Critical Dimension Etch 2002 Updates and 2003 Projects

  13. Critical Dimension Etch • Working Group Co-Chairs – Adrian Kiermasz- Lam Research • - Rob Kraft- TI • Key Near Term Difficult Challenges Linked to Etch • 10% 3 Channel Length Control with standard gate stack materials • 10% 3 Channel Length Control with high-k, dual metal gate stacks • Achievement of channel length control where the etched feature size is smaller than the feature size printed in the resist.

  14. Critical Dimension Etch • Key Long Term Difficult Challenges Linked to Etch • 10% 3 Channel Length Control with standard gate stack and with high-k, dual metal gate stacks • Achievement of channel length control where the etched feature size is smaller than the feature size printed in the resist. • Channel length control for non-standard, double gate devices

  15. Critical Dimension Etch - 2002 Updates and 2003 Projects • No year 2002 updates • 2003 Projects- See posters for greater detail • Upgrade resist trim and etch CD requirements assuming new variance budget with Lithography • Variance allocation had been 2/3 litho, 1/3 etch, proposed to change to 4/5 litho, 1/5 etch • Add Shallow Trench Isolation Etch requirements • Add CD control with evolving gate stack materials and structures • Guidance on etch equipment repeatability for gate etch • Persons interested in 2003 project participation see Posters for sign-up instructions

  16. Thermal Films 2002 Updates and 2003 Projects

  17. Thermal Films • Working Group Co-Chairs – Carlton Osburn- NCSU • - Howard Huff- Int’l Sematech • Key Near Term Difficult Challenges Linked to Thermal Films • Extension of Oxynitride gate dielectric materials to <1nm EOT • Introduction and process integration of high-k gate dielectric layers • Potential introduction of CMOS dual metal gate electrodes • Key Long Term Difficult Challenges Linked to Thermal Films • Introduction and process integration of higher-k gate dielectric layers • Metal gate electrodes with appropriate work function • Enhanced channel mobility with strained layer silicon • Introduction of non-standard double gate MOSFET devices

  18. Thermal Films - 2002 Updates and 2003 Projects • 2002 Updates-See Posters for Details • Correct table construction errors • Update PMD via diameters and aspect rations to remove inconsistency with lithography • 2003 Projects • Re-examine gate leakage requirements in collaboration with PIDS and Design TWGs • Generation of model for smooth, scaled, EOT values • Shallow trench isolation (fill) requirements • Persons interested in participating on 2003 projects see posters for sign-up instructions

  19. Transistor Doping 2002 Updates and 2003 Projects

  20. Transistor Doping • Working Group Co-Chairs –Larry Larson, Int’l Sematech - Doug Mercer, TI • Key Near Term Difficult Challenges Linked to Doping • Achievement of source/drain contact structures that exhibit less than 16-20% of overall MOSFET channel resistance • Achievement of doped polysilicon gates that show activated doping concentrations that are above the solubility limit (metastable doping) • Formation of continuous self aligned silicide contacts over very shallow contact junctions • Key Long Term Difficult Challenges Linked to Thermal Films • Formation of low resistivity contacts on ultra-scaled planar MOSFETS • Low resistivity contact formation on non-standard, double gate MOSFET devices

  21. Doping - 2002 Updates and 2003 Projects • 2002 Updates-See Posters for Details • Correction of table text errors • Correction of out-year polysilicon doping errors • Add- Drain extension sheet resistance requirements for N-channel MOSFET • 2003 Projects- See Posters for Details • Collaborate with PIDS to produce improved MOSFET source/drain resistance model • Re-visit polysilicon depletion model • Review and add new potential solution technologies • Persons interested in participating on 2003 projects see posters for sign-up instructions

  22. Memory FEP Processes 2002 Updates and 2003 Projects

  23. Memory • DRAM Lead TWG’s –Stack Capacitor- Japan FEP/PIDs – Y.Takeda, Sanyo - Trench Capacitor – Europe FEP/PIDS- B. Vollmer, Infineon • Flash Memory Lead TWG’s – (NOR) Europe FEP/PIDS- M. Alessandri, STM • - (NAND) Korea FEP/PIDS- H. Kang, Samsung • FeRAM Lead TWG- Japan FEP/PIDS- M. Kubota, Sony • Key Near Term Difficult Challenges Linked to Memory FEP Processes • CMOS integration of new memory materials and processes • High dielectric constant materials (Flash Memory) • Very high dielectric constant materials (DRAM) • Ferroelectric materials (FeRAM) • Material temperature sensitivity requires low temperature CMOS integration • Key Long Term Difficult Challenges Linked to Memory FEP processes • New memory storage cells, storage devices, and memory architectures

  24. Flash Memory - 2002 Updates and 2003 Projects • 2002 Updates-See Posters for Details • Multiple requirements changes due to 1-year roadmap pull-in • Updated NAND tunnel and interpoly dielectric layers • 2003 Projects- See Posters for Details • Concentrate on Flash potential solutions • Red walls loom on tunnel and interpoly EOT • Other Projects TBD • The Flash TWG is eagerly looking for US participants to participate in year 2003 projects. Interested parties should leave their business cards at the FEP poster boards.

  25. DRAM Trench - 2002 Updates and 2003 Projects • 2002 Updates-See Posters for Details • Storage capacitor structures updated in order to achieve higher capacitance • 2003 Projects • Concentrate on DRAM trench capacitor potential solutions • Other Projects TBD • The DRAM Trench Capacitor TWG is eagerly looking for participants to participate in year 2003 projects. Interested parties should leave their business cards at the FEP poster boards.

  26. DRAM Stack - 2002 Updates and 2003 Projects • 2002 Updates • No updates planned • 2003 Projects • Concentrate on DRAM stack capacitor potential solutions • Other Projects TBD • The DRAM Stack Capacitor TWG is eagerly looking for participants to participate in year 2003 projects. Interested parties should leave their business cards at the FEP poster boards.

  27. FeRAM - 2002 Updates and 2003 Projects • 2002 Updates • No updates planned • 2003 Projects • Concentrate on developing requirements and potential solutions needed for continued scaling of the FeRAM storage cell • The FeRAM TWG is eagerly looking for participants to participate in year 2003 projects. Interested parties should leave their business cards at the FEP poster boards.

  28. 2002 Update Summary • Flash roadmap accelerated by one year • DRAM Trench capacitor structures changed • Potential Changes to DRAM stack capacitor “a” value • Added NMOS drain extension doping requirements • Error correction and footnote text editing • Open issue: wafer edge exclusion dimension

  29. 2003 Program Summary • Concentrate on memory cell scaling and potential solutions • Updated gate leakage models and requirements forecasts • Updated MOSFET source/drain resistance models and forecasts • Updated polysilicon depletion models and doping forecasts • Updated CD etch requirements based on new variance budget allocation between litho and etch • STI etch and fill requirements and potential solutions • Updated SOI requirements and potential solutions, including Si:Ge on buried oxide • Requirements and potential solutions for next generation silicon substrate (450mm?) • Surface Prep coordinate with other TWG’s to achieve consistent defectivity models and metrics

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