JK Flip-Flop

1. JK Flip-Flop

2. Q J K Q J K C Qn+1 0 0 ­ Qn Hold 0 1 ­ 0 Reset 1 0 ­ 1 Set 1 1 ­ Qn Toggle X X X Qn Hold JK Flip-flop • The most versatile of the flip-flops • Has two data inputs (J and K) • Do not have an undefined state like SR flip-flops • When J & K both equal 1 the output toggles on the active clock edge • Most JK flip-flops based on the edge-triggered principle +ve edge triggered JK flip-flop • The C column indicates +ve edge triggering (usually omitted)

3. J K C Qn+1 0 0 ­ Qn Hold 0 1 ­ 0 Reset 1 0 ­ 1 Set 1 1 ­ Qn Toggle X X X Qn Hold Example JK circuit J Q A C E Ck F D B ~Q K • Assume Q = 0, ~Q = 1, K = 1 • Gate B is disabled (Q = 0, F = 1) • Make J = 1 to change circuit, when Ck = 1, all inputs to A = 1, E goes to 0, makes Q = 1 • Now Q and F are both 1 so ~Q = 0 and the circuit has toggled.

4. Timing diagram for JK Flip-flop Negative Edge Triggered clock J K Q toggle J=K=1 hold J=K=0 reset J= 0 K=1 set J= 1 K=0

5. Clock Pulse • The JK flip flop seems to solve all the problems associated with both inputs at 1. • However the clock rise/fall is of finite duration. • If the clock pulse takes long enough, the circuit can toggle. • For the JK flip flop it is assumed the pulse is quick enough for the circuit to change only once. ideal / actual edge pulse

6. JK from D Flip-flop J Q D K CLK C Q’

7. Master-Slave JK Flip-flop • The Master-Slave Flip-Flop is basically two JK bistable flip-flops connected together in a series configuration with the outputs from Q and Q from the "Slave" flip-flop being fed back to the inputs of the "Master" with the outputs of the "Master" flip-flop being connected to the two inputs of the "Slave" flip-flop as shown below.

9. Cont.., • The input signals J and K are connected to the "Master" flip-flop which "locks" the input while the clock (Clk) input is high at logic level "1". • As the clock input of the "Slave" flip-flop is the inverse (complement) of the "Master" clock input, the outputs from the "Master" flip-flop are only "seen" by the "Slave" flip-flop when the clock input goes "LOW" to logic level "0". • Therefore on the "High-to-Low" transition of the clock pulse the locked outputs of the "Master" flip-flop are fed through to the JK inputs of the "Slave" flip-flop making this type of flip-flop edge or pulse-triggered.

10. Cont.., • Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip-flop is a "Synchronous" device as it only passes data with the timing of the clock signal.

11. J-K Flip-Flop Data Transfer • In synchronous data transfer between two J-K flip-flops, a transfer signal on the clock input causes transfer from cell A to cell B. The transfer signal could be applied to several such cells in series to create a shift register.

12. Cont.., • In asynchronous data transfer, a transfer pulse may be applied at any time to force the data onto the asynchronous set and clear inputs, storing the data regardless of what is happening on the other inputs.

13. Characteristics of JK flip-flop • If one input (J or K) is at logic 0, and the other is at logic 1, then the output is set or reset (by J and K respectively), just like the RS flip-flop, but on the (falling) clock edge. • If both inputs are 0, then it remains in the same state as it was before the clock pulse occurred; again like the RS flip flop. • If both inputs are high, however the flip-flop changes state whenever the (falling) edge of a clock pulse occurs; i.e., the clock pulse toggles the flip-flop.

14. See also • http://www.brighthub.com/engineering/electrical/articles/46610.aspx • http://www.electronics-tutorials.ws/sequential/seq_2.html • http://www.wisc-online.com/objects/ViewObject.aspx?ID=DIG3303 • http://computer.howstuffworks.com/boolean5.htm