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entity PROB1 is port ( DIN: in BIT_VECTOR (7 downto 0);

Exercise Syntax Check. entity PROB1 is port ( DIN: in BIT_VECTOR (7 downto 0); DOUT: out BIT_VECTOR (7 downto 0) ); end PROB1; architecture PROB1 of PROB1 is begin variable i : integer := 0; variable stop : integer := 7;

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entity PROB1 is port ( DIN: in BIT_VECTOR (7 downto 0);

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  1. Exercise Syntax Check entity PROB1 is port ( DIN: in BIT_VECTOR (7 downto 0); DOUT: out BIT_VECTOR (7 downto 0) ); end PROB1; architecture PROB1 of PROB1 is begin variable i : integer := 0; variable stop : integer := 7; i := 0; loop1 : while DIN(i) != 1 DOUT(i) := DIN(i); i := i + 1; exit loop1 when i := stop; end loop loop1; loop2 : while i != stop DOUT(i) := not DIN(i); i := i + 1; end loop loop2; end PROB1; EE514

  2. Exercise Syntax Check entity PROB1 is port ( DIN: in BIT_VECTOR (7 downto 0); DOUT: out BIT_VECTOR (7 downto 0) ); end PROB1; architecture PROB1 of PROB1 is begin p0: process variable i : integer := 0; variable stop : integer := 7; begin i := 0; loop1 : while DIN(i) /= ‘1’ DOUT(i) <= DIN(i); i := i + 1; exit loop1 when i = stop; end loop loop1; loop2 : while i/= stop DOUT(i) <= not DIN(i); i := i + 1; end loop loop2; end process; end PROB1; EE514

  3. Chapter 7Design unit, library & configuration • Architecture • Entity declaration • Port map and generic map • Configuration • Design unit • VHDL library • Block and architecture attributes • Exercises EE514

  4. Architecture Architecture_body::= architecture identifier of entity-name is architecture_declaration_part begin [concurrent statements] end [architecture_simple_name] EE514

  5. Entity declaration Entity_declaration::= entity identifier is [generic(generic_list);] [port(port_list);] entity_declarative_part [begin entity_statement_part] end[entity_simple_name] EE514

  6. Entity declaration library IEEE; use IEEE.std_logic_1164.all; entity DFF is generic ( PRESET_CLRn : in integer); port ( RSTn, CLK, D : in std_logic; Q : out std_logic); end DFF; architecture RTL of DFF is begin process (RSTn, CLK) begin if (RSTn = '0') then if (PRESET_CLRn = 0) then Q <= '0'; else Q <= '1'; end if; elsif (CLK'event and CLK = '1') then Q <= D; end if; end process; end RTL; EE514

  7. Entity declaration library IEEE; use IEEE.std_logic_1164.all; entity SHIFTN is generic ( PRESET_CLRn : in integer; N : in integer); port ( RSTn, CLK, SI : in std_logic; SO : out std_logic); signal T : std_logic_vector(N downto 0); begin assert (N > 3) and (N < 33) report "N outside of range 4 to 32"; end SHIFTN; EE514

  8. Entity declaration Component_declaration::= component identifier [generic(generic_list);] [port(port_list);] end component; Generic is a good way to pass parameters like bus width, delay, fine name, e.t.c. to a design entity EE514

  9. Entity declaration architecture RTL of SHIFTN is component DFF generic ( PRESET_CLRn : in integer); port ( RSTn, CLK, D : in std_logic; Q : out std_logic); end component; begin g0 : for i in N-1 downto 0 generate g1 : if (i = N-1) generate bit7 : DFF generic map (PRESET_CLRn => PRESET_CLRn) port map (RSTn => RSTn, CLK => CLK, D => SI, Q => T(N-2)); end generate; g2 : if (i > 0) and (i < N-1) generate bitm : DFF generic map (PRESET_CLRn => PRESET_CLRn) port map (RSTn, CLK, T(i), T(i-1)); end generate; g3 : if (i = 0) generate bit0 : DFF generic map (PRESET_CLRn => PRESET_CLRn) port map (RSTn, CLK, T(0), SO); end generate; end generate; end RTL; EE514

  10. Entity declaration The same functionality is obtained by the following code architecture RTL1 of SHIFTN is component DFF generic ( PRESET_CLRn : in integer); port ( RSTn, CLK, D : in std_logic; Q : out std_logic); end component; begin T(N) <= SI; SO <= T(0); g0 : for i in N-1 downto 0 generate allbit : DFF generic map (PRESET_CLRn => PRESET_CLRn) port map (RSTn => RSTn, CLK => CLK, D => T(i+1), Q => T(i)); end generate; end RTL1; EE514

  11. Entity declaration Synthesized with N mapped to 5 and PRESET_CLRn to 0 Synthesized with N mapped to 3 and PRESET_CLRn to 1 EE514

  12. Dilbert EE514

  13. Port map and generic map library IEEE; use IEEE.std_logic_1164.all; entity BUF is port ( RSTn, CLK, J, K : in std_logic; Q : buffer std_logic); end BUF; architecture RTL of BUF is begin p0 : process (RSTn, CLK) begin if (RSTn = '0') then elsif (CLK'event and CLK = '1') then if (J = '1') and (K = '1') then Q <= not Q; elsif (J = '1') and (K = '0') then Q <= '1'; elsif (J = '0') and (K = '1') then Q <= '0'; end if; end if; end process; end RTL; EE514

  14. Port map and generic map library IEEE; use IEEE.std_logic_1164.all; entity BUFMAP is port ( RSTn, CLK, DA, DB : in std_logic; DOUT : out std_logic); end BUFMAP; architecture RTL of BUFMAP is component BUF port ( RSTn, CLK, J, K : in std_logic; Q : buffer std_logic); end component; begin buf0 : BUF port map ( RSTn => RSTn, CLK => CLK, J => DA, K => DB,Q => DOUT); -- ERROR!! map mode buffer with mode out end RTL; EE514

  15. Configuration configuration_declaration::=configuration identifier of entity_name is {use_clause|attribute_specification} {block_configuration} end[configuration_simple_name] block_configuration::= for block_specification {use_clause}{block_configuration| component_configuration} end for; block_specification ::= architecture_name [block_statement_label | generate_statement_label[(discrete_range | static_expression )] EE514

  16. Configuration configuration CFG_RTL2_SHIFT of SHIFT is for RTL2 for g0 for g1 for all : DFF use configuration WORK.CFG_RTL_DFF; end for; end for; for g2 for all : DFF use entity WORK.DFF(RTL); end for; end for; for g3 for bit0 : DFF use entity WORK.DFF(RTL); end for; end for; end for; end for; end CFG_RTL2_SHIFT; Examples of configuration generate statement labels configuration CFG_RTL_DFF of DFF is for RTL end for; end CFG_RTL_DFF; configuration CFG_RTL1_SHIFT of SHIFT is for RTL1 for all : DFF use entity WORK.DFF(RTL); end for; end for; end CFG_RTL1_SHIFT; block configuration instantiation label component configuration binding indication EE514

  17. Configuration configuration CFG_RTL3_SHIFT of SHIFT is for RTL3 for g0 (2 downto 0) for allbit : DFF use configuration WORK.CFG_RTL_DFF; end for; end for; for g0 (7 downto 4) for all : DFF use configuration WORK.CFG_RTL_DFF; end for; end for; for g0 (3) for allbit : DFF use entity WORK.DFF(RTL); end for; end for; end for; end CFG_RTL3_SHIFT; Generate statement labels EE514

  18. Configuration end for; end for; for stage1 : SHIFT use configuration WORK.CFG_RTL2_SHIFT; end for; for stage2 : SHIFT use configuration WORK.CFG_RTL3_SHIFT; end for; end for; end CFG_RTL5_SHIFT24; configuration CFG_RTL5_SHIFT24 of SHIFT24 is for RTL5 for stage0 : SHIFT use entity WORK.SHIFT(RTL1); for RTL1 for all : DFF use entity WORK.DFF(RTL); end for; instantiation labels Hierarchical configuration EE514

  19. Configuration configuration CFG_RTL5_BLOCKSTMT of BLOCKSTMT is for RTL5 for stage2 : SHIFT use configuration WORK.CFG_RTL1_SHIFT; end for; for block0 for stage1 : SHIFT use configuration WORK.CFG_RTL2_SHIFT; end for; for stage0 : SHIFT use configuration WORK.CFG_RTL3_SHIFT; end for; end for; end for; end CFG_RTL5_BLOCKSTMT; block label component instantiation EE514

  20. Configuration • Soft binding by the configuration specification is preferred if several architectures are associated with the same entity • Separate configurations using different architecture bindings can be compiled once • During simulation different configurations can be selected without recompiling the VHDL source code EE514

  21. Configuration library IEEE; use IEEE.std_logic_1164.all; entity SHIFT8 is port ( RSTn, CLK, SI : in std_logic; SO : out std_logic); signal T : std_logic_vector(8 downto 0); end SHIFT8; architecture RTL1 of SHIFT8 is component DFF -- generic ( ) -- PRESET_CLRn : in integer); port ( -- generic map in the configuration -- will be used to reset SHIFT8 -- to the initial value 01010011 RSTn, CLK, D : in std_logic; Q : out std_logic); end component; constant N : integer := 8; begin T(N) <= SI; SO <= T(0); g0 : for i in N-1 downto 0 generate allbit : DFF -- generic map (PRESET_CLRn => 1) port map (RSTn => RSTn, CLK => CLK, D => T(i+1), Q => T(i)); end generate; end RTL1; EE514

  22. Configuration configuration CFG_RTL1_SHIFT8 of SHIFT8 is for RTL1 for g0 (1 downto 0) for allbit : DFF use entity WORK.DFF(RTL) generic map (PRESET_CLRn => 1); end for; end for; for g0(6) for allbit : DFF use entity WORK.DFF(RTL) generic map (PRESET_CLRn => 1); end for; end for; for g0(4) for allbit : DFF use entity WORK.DFF(RTL) generic map (PRESET_CLRn => 1); end for; end for; for g0 (3 downto 2) for all : DFF use entity WORK.DFF(RTL) generic map (PRESET_CLRn => 0); end for; end for; for g0(7) for all : DFF use entity WORK.DFF(RTL) generic map (PRESET_CLRn => 0); end for; end for; for g0(5) for all : DFF use entity WORK.DFF(RTL) generic map (PRESET_CLRn => 0); end for; end for; end for; end CFG_RTL1_SHIFT8; EE514

  23. Design unit • A design file can have one or many design units. • The primary design unit can be either entity declaration, configuration declarations, or package declarations. • A VHDL primary design unit can be associated with many secondary design units that include an architecture body and a package body. • Each primary unit in a given library must have a unique simple name. • Each architecture body associated with a given entity declaration must be unique. EE514

  24. VHDL library Working library WORK is the library in which the design unit is placed Every design unit is assumed to have the following implicit statements: library STD, WORK; use STD.STANDARD.all; EE514

  25. VHDL library EE514

  26. VHDL library Library_clause::=library logical_name {,logical_name}; library COMP_LIB; configuration CFG1_RTL1_SHIFT of SHIFT is for RTL1 for bit7, bit6, bit4 : DFF use entity COMP_LIB.DFF(RTL); end for; for bit2 : DFF use entity WORK.DFF(RTL); end for; for others : DFF use configuration WORK.CFG_RTL_DFF; end for; end for; end CFG1_RTL1_SHIFT; EE514

  27. Block and architecture attributes A predefined attribute BEHAVIOR (ENT’ behavior) is TRUE if there are not component instantiation statements inside the associated block statement or architecture. Attribute STRUCTURE (ENT’structure) is TRUE within the block or architecture if all process statements or equivalent process statements ( concurrent statements) do not contain signal assignment statement. EE514

  28. Dilbert EE514

  29. Find libraries and packages underAldec Active VHDL EE514

  30. Find source codes in Projects EE514

  31. For review use tutorial Evita EE514

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