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SLAAC Hardware Status Brian Schott

SLAAC Hardware Status Brian Schott. Provo, UT September 1999. One Xilinx 4085 and two Xilinx 40150s. 750K user gates Twelve 256Kx18 ZBT SSRAM memories. 72-bit ring busses and crossbar bus Xilinx 4062 PCI interface. Two 72-bit FIFO ports. External memory bus. 100MHz programmable clock.

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SLAAC Hardware Status Brian Schott

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  1. SLAAC Hardware StatusBrian Schott Provo, UT September 1999

  2. One Xilinx 4085 and two Xilinx 40150s. 750K user gates Twelve 256Kx18 ZBT SSRAM memories. 72-bit ring busses and crossbar bus Xilinx 4062 PCI interface. Two 72-bit FIFO ports. External memory bus. 100MHz programmable clock. X1 X2 X0 IF  SLAAC1 Architecture 72/ 72 /

  3. Memory Module SLAAC1 Front SLAAC-1 PCI

  4. SLAAC-1 Back QC64 I/O

  5. 7 SLAAC-1 Rev A boards operational: 1 to BYU (1) 1 to UCLA (0) 1 to ISI (0) 0 to LANL (2) 0 to VT (1) Hardware works! A few jumper wires for new features and fixes. 32-bit 33MHz Xilinx PCI core Mailbox FIFOs to 70MHz Software NT device driver Command-line debugger C++ node layer library VHDL simulation + synthesis JHDL? SLAAC-1 Rev A Status

  6. Rev B Differences Jumper changes from Rev A incorporated into board Power cycle on clock chip Soft reset to boot IF chip Clock nets split Changed PAL to XC9500 Using single EEPROM LED footprint & sequence X0 gets two new LEDs! Delivery Strategy Bare boards (10) at ISI now. Waiting for Xilinx order (promised in 2 weeks). Rev A is OK for now. Expect to swap out with Rev B over next several months. Recover FPGAs from Rev A. Outside Customers DoD (2), DEFACTO (?), GMU(?) SLAAC-1 Rev B SLAAC Hardware Status

  7. Current Revision Using Xilinx core for 32-bit 33MHz PCI. One input and one output “mailbox” 1-deep FIFOs. Configure, set clock, run/stop clock and other basic functions. SLAAC-1 memories mapped into host address space. Next Revision Readback support. 4 input and 4 output FIFOs. Single step and count down clock timers. Handshake register halt mask and interrupt mask. Software EEPROM programming. Future DMA engine SLAAC-1 PCI Interface

  8. FIFOs in IF chip. X0 can select from four input and four output FIFOs on FIFOA and FIFOB ports. FIFOs are 68 bits (4-bit tag) DMA engine monitors FIFO states and copies data to/from host buffers. This is much more efficient than host-based accesses because no back pressure is needed. FIFO Model X0 A B IF         DMA PCI core

  9. Each node/system has a set of FIFO buffers. Channels connect two FIFO buffers. Arbitrary streaming-data topologies supported. ACS_Enqueue() put user data into FIFO ACS_Dequeue() get user data from FIFO FIFO 0 FIFO 0 FIFO 1 FIFO 1 FIFO 2 FIFO 2 FIFO 3 FIFO 3 Streaming Data Functions 1 FIFO 0 0 FIFO 1 FIFO 2 2 FIFO 3

  10. Splash-2-like VHDL simulator supports 4 input and 4 output FIFO textIO files memory initialization files JHDL model? Device Driver NT available. Linux driver started, but somebody needs to push us to make it a priority. ACS Node Layer Library implemented in C++ not yet integrated with System layer API (SLAAC-1 added some methods) Command Line Debugger T2 like CLI for controlling a SLAAC-1 board. SLAAC-1 Software

  11. Two “independent” SLAAC1 boards in single 6U VME mezzanine. Four XC40150s, two XC4085s - 1.5M gates total. Twenty 256Kx18 SSRAMs. Sacrificed external memory bus. X1 X2 X1 X2 X0 X0 IF IF   PowerPC Bus A PowerPC Bus B SLAAC2 Architecture 40 / 40 / 72/ 72/

  12. SLAAC2 Front

  13. SLAAC-2 Back

  14. CSPI M2641S • 2 - PPC603/740 @ 200 MHz. • 40MHz PPC Bus • Integrated Myrinet SAN network

  15. 3 SLAAC-2 boards: 2 with all XC4085s, 1 is stable for demos 1 is rigged for download cable on bench 1 with XC40150s and 64K memories Intermittent problem booting IF node B. Plan to recover FPGAs. Things to fix: Clock generator frequency programming not reliable. Address and data lines are swapped on all memories! Not bitfile compatible with SLAAC-1 board SLAAC 2 Status

  16. Rev A Differences Changes from S1B and S2 incorporated into board Power cycle on clock chip Soft reset to boot IF chip Clock nets improved Memory pin assignment Changed PAL to XC9500 Using single EEPROM LED footprint & sequence Each X0 gets two new LEDs! Delivery Strategy 1 assembled board under test (XC40150, 256Kx18) 9 bare boards at ISI. Waiting for Xilinx order (2 weeks). Assemble 3 more: 1 to Sandia 1 to LMGES 1 to NVL Recover S2 FPGAs and build more for outside customer (ADAPTERS). SLAAC-2 Rev A

  17. Interface Using VHDL PowerPC core created by CSPI. At same level of capability as SLAAC-1. Since SLAAC-1 is easier to work with, we plan to build most new modules there and port over to SLAAC-2. Software Command-line debugger based on old TSDB. ‘C’ Control library for VxWorks has not yet been ported to node layer library. Plan is to port to node layer library for S2 and port S1 debugger. No option for other operating systems. SLAAC-2 Interface & Software

  18. SLAAC-1 7 Rev A boards available right now, 10 Rev B boards assembled in few weeks We plan to swap out existing Rev A boards with Rev B and recover parts over next few months. Interface is functional, but not complete. Software is functional, but not complete either. SLAAC-2 1 SLAAC-2 is available for “supervised” demos. 1 Rev A board has been assembled and is under test. Plans are to build 3 more for SLAAC team and deliver in a few weeks. Interface is functional, but not complete. Software is functional, but not complete either. Hardware Summary

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