Workshop on the Testing of High Resolution Mixed Signal Interfaces

1. Workshop on the Testing of High Resolution Mixed Signal Interfaces Held in conjunction with the European Test Symposium 2004Sunday 23rd May 2004Danielle Casanova Room, Congress Center AJACCIO, Corsica Sponsored by Fr. V-IST project 34283 “Testability of Analogue Macrocells Embedded in System-on-Chip” TAMES-2

2. TAMES2 : addressing embedded high Resolution Analog Macro Cells Test Challenges Christophe Gaillard Dolphin Integration, France

3. Objectives • The work will respond to three key industrial demands: • Test cost reduction through minimization of test time and test development cost • Improvements in test coverage and outgoing quality, to address the industrial trend for higher quality product at lower cost. • Development of test reuse concepts and integration of the associated advances in test engineering into the design flow for new interface designs in SoC applications.

4. KEY FIGURES, PARTNERS 2.5 Years Project Duration 4 Partners (2 academic, 2 industrial) DOLPHIN Integration

5. Description of the work : main steps • The work to be carried out to achieve the advances proposed in converter test engineering will be driven by industrial user’s requirements. • Themain steps of the TAMES-2 project are proposed in the following slides

6. Study of the requirements for industrial mixed-signal test • A detailed review of test strategies for HR converters has been carried out. • Reference test plans have been worked out • Circuit level failure mode analysis, correlation with design specification • Specification testing effectiveness

7. Definition of suitable innovative Test Techniques • Innovative Test Techniques have been studied using both BIST and black box approaches • Decision Matrix : a tool for performance evaluation and comparison was developed to provide a rational metrics

8. Validation of the objectives through the design of industrial SIP • an audio codec and an automotive interface, both representing macrocells for use in much larger SoC designs and having complementary test requirements. • this design includes specification and architecture of the SIP blocks, development of robust schematics for the analogue part • implementation of DfT techniques and layout in advanced CMOS processes

9. Design and fabrication of test chips including the two SIP blocks Stereo ADC 45 kgates Digital section w/ spRAM Stereo DAC CODEC Demonstrator 25 mm2

10. Characterization and test of the testchips • Characterization • laboratory test benches • efficiency of the DfT solutions • performances of the SIP blocks

11. Use Plan • Use of the SIP blocks • by AMI Semiconductors • by Dolphin through inclusion in its SIP catalogue • This will include the packaging of the test techniques to allow usage by SoC integrators

12. Dissemination of results • Result dissemination through academic courses and international conferences • Web site • http://www.imse.cnm.es/tames2

13. Decision Matrix Open tool for Test Techniques evaluation and comparison

14. Outline • Purpose and goal • List of Criteria • Explanation of some key criteria • Example of Decision Matrix • Alternative Test Plan

15. Decision Matrix • Goal • Measure the impact and performance of the studied Test Techniques • Assess the Test Techniques relevance with respect to a reference test plan • Assess the Test Techniques relevance against TAMES2 targets • Cost computation

16. Decision Matrix : 9 criteria • 1. Test time in second • 2. Penalty for the test of the rest of the SoC • 3. Test cost saving • 4. Silicon area overhead in sq.mm. • 5. Cost of the test solution • 6. Cost of design and risk of degradation of performance • 7. Packaging of Test Technique • 8. Package over cost due to additional pins • 9. Specification/functional coverage

17. 1. Test time in second • Time required to perform a test or set of tests • Parameters • Test time: acquisition + transfer + computation • Cost per second of the industrial tester

18. 2. Penalty for the test of the rest of the SoC • The analog ViC insertion may prevent usage of pure digital tester • Therefore this bring a cost penalty due to higher cost for mixed signal tester • Parameters • Estimated SoC test duration (default value is 2 s) • Cost per second of the industrial tester

19. 4. Silicon area overhead in mm2 • On chip requirements for test implementation may introduces silicon area overhead • Parameters • Estimated silicon area overhead • Cost of silicon per mm2 (default value is 10 cts/mm2)

20. 7. Packaging of Test Technique • The test technique must be properly documented to allow its usage by SoC integrator. • Test specification (hardware and software requirements) • Application notes • Models including the test technique • Parameters • Estimated man power, Cost of man power

21. Example of Matrix

22. Alternative Test Plan • Will be build using new T.T. according to a given test strategy

23. Example of cost savings 16.8 cts / device are saved!

24. Conclusions • Decision Matrix is a general and open tool: parameters must be considered from today’s perspective and shall be reviewed according to technological progress • Test strategy will drive the usage of given T.T. and use the Matrix as decision tool • The reference testplan may be simplified during production after a learning curve or an intensive characterization of samples and correlation with standard measurements. The proposed Test techniques may play a significant role in this simplification. • In the market of Virtual Component, the customers are very sensitive to the ease of use of the proposed solution, e.g. BIST (they have often no skill in the field of analog test) even if the test time is higher. The decision parameters need then to be adjusted accordingly

25. That’s it … Thank You!