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VLSI Design Chapter 5 CMOS Circuit and Logic Design

VLSI Design Chapter 5 CMOS Circuit and Logic Design. Jin-Fu Li. Chapter 5 CMOS Circuit and Logic Design. CMOS Logic Gate Design Physical Design of Logic Gates CMOS Logic Structures Clocking Strategies I/O Structures Low-Power Design. Logic Gate Design Issues. Hierarchical design

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VLSI Design Chapter 5 CMOS Circuit and Logic Design

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  1. VLSI DesignChapter 5 CMOS Circuit and Logic Design Jin-Fu Li

  2. Chapter 5 CMOS Circuit and Logic Design • CMOS Logic Gate Design • Physical Design of Logic Gates • CMOS Logic Structures • Clocking Strategies • I/O Structures • Low-Power Design EE613 VLSI Design

  3. Logic Gate Design Issues • Hierarchical design • Architecture level • RTL/logic gate level • Circuit level • Layout level • Critical paths – the path with the longest delay that require attention to timing details • The number of Fanins and Fanouts affects the performance of the circuits EE613 VLSI Design

  4. Concept of Fanin and Fanout • Fanin • The fanin of any complex gate is defined as the number of inputs of this gate • Fanout • The fanout of a complex gate is defined as the number of driven inputs attached to the output of this gate N N Fanout=N Fanin=N EE613 VLSI Design

  5. Logic Gate Design – NAND Gate • Rp= the effective resistance of p-device in a minimum-sized inverter • n = width multiplier for p-devices in this gate • k = the fanout • m = fanin of gate • Cg = gate capacitance of a minimum-sized inverter • Cd= source/drain capacitance of a minimum-sized inverter • Cr= routing capacitance EE613 VLSI Design

  6. Logic Gate Design – Fanins and Fanouts EE613 VLSI Design

  7. Logic Gate Design – NAND Gate Rise Time Separate delay into internal delay and external delay caused by fanouts EE613 VLSI Design

  8. Logic Gate Design – NAND Gate Fall Time We want the rise time to be equal to the fall time Hence we must design , thus the delay time is EE613 VLSI Design

  9. A B C D NR4-Rise 10.0 ns 10.0 ns ND4-Fall ND4-Rise NR4-Fall A B C D 0.0 0.25 0.5 0.75 1.0 0.0 0.25 0.5 0.75 1.0 Typical CMOS NAND & NOR Delays Delay (ns) Delay (ns) Capacitive load (pf) Capacitive load (pf) EE613 VLSI Design

  10. NAND- and NOR-Gates Delays Measured with SPICE tinternal-r (ns) toutput-r (ns/pf) tinternal-f (ns) GATE toutput-f (ns/pf) INV ND2 ND3 ND4 ND8 NR2 NR3 NR4 NR8 1.7 3.1 4.4 5.7 10.98 1.75 1.83 1.88 1.8 .08 .2 .41 .68 2.44 .135 .14 .145 .19 .08 .15 .2 .25 .38 .25 .52 .9 3.35 2.1 2.1 2.1 2.1 2.2 4.1 6.2 8.2 16.4 Logic Gate Design – Gate Delays EE613 VLSI Design

  11. Efficient Resistance Value for a Typical 1u CMOS Process Rn ( ) GATE Rp ( ) INV ND2 ND3 ND4 NR2 NR3 NR4 7.1K 6.3K 6.0K 5.9K 7.3K 7.4K 7.5K 8.5K 8.6K 8.7K 8.8K 8.4K 8.4K 8.4K Logic Gate Design – Efficient Resistance EE613 VLSI Design

  12. Logic Gate Design – 8-Input AND Gate A B C D E Approach 1 CL F G H A B C D Approach 2 E CL F G H A B C D E Approach 3 F CL G H EE613 VLSI Design

  13. Comparison of Approaches to Designing an 8-Input AND Gate Delay Stage 2ns Delay Stage 3ns Total Delay (SPICE) ns Delay Stage 1ns Delay Stage 4ns Approach 3.37 INV rising 2.82 ND8 falling 1 ND8->INV 6.2 (6.5) .88 ND4 falling 4.36 NR2 rising 2 ND4->NR2 5.24 (5.26) 3 ND2->NR2 ND2->INV .31 ND2 falling .4 NR2 rising .31 ND2 falling 2.17 INV rising 3.19 (3.46) Logic Gate Design – 8-Input AND Gate EE613 VLSI Design

  14. Basic Physical Design • Gates: Inverter, NAND, and NOR • Complex Gates • Standard Cells • Gate Array • Sea of Gates • Layout Optimization • Transmission Gates • 2-Input Multiplexer EE613 VLSI Design

  15. Physical Design – CMOS Inverter Vdd Vdd a z a z Vss Vss EE613 VLSI Design

  16. Physical Design – NAND Gate Vdd Vdd z a z b a b Vss Vss EE613 VLSI Design

  17. Physical Design – NOR Gate Vdd Vdd a z z b Vss Vss b a EE613 VLSI Design

  18. Physical Design – Complex Gates • All complex gates can be designed using a single row of N-transistors and a single row of P-transistors, aligned at common gate connections • Design procedure • Draw two dual graphs to P transistor tree and N transistor tree • Find all Euler paths that cover the graph • Find a P and an N Euler path that have identical labeling • If not found, break the gate in the minimum numbers of places to achieve step 3 EE613 VLSI Design

  19. Physical Design – Complex Gates VDD C D D Vss Z C I1 I3 B I1 I2 A B Z I2 C A B A I3 Z D EE613 VLSI Design

  20. Physical Design – Complex Gates D C D C B B A A Vdd z Vss A B C D EE613 VLSI Design

  21. Physical Design – XNOR Gate (1) A Z’ B Z Vdd A Z’ Z’ z B A B Z’ Vss A B EE613 VLSI Design

  22. Physical Design – XNOR Gate (2) A B Z Vss Vdd z B A EE613 VLSI Design

  23. Physical Design – Automated Approach A B D E C Vdd A E C B D E Vss D E A B D E A B C C Vdd P N Vss EE613 VLSI Design

  24. Physical Design – Standard-Cell Approach WVdd Wp Dnp Wn a b c d z WVss EE613 VLSI Design

  25. Physical Design – Standard-Cell Layout Vdd Vdd Vss Vss a b c z z a b c EE613 VLSI Design

  26. Physical Design – Gate Array Layout (1) Vdd Vss EE613 VLSI Design

  27. Physical Design – Gate Array Layout (2) Vdd Gate array cells Routing channels Vss EE613 VLSI Design

  28. Physical Design – Sea-of-Gate Layout well contacts Vdd supply P-transistors poly gates N-transistors supply Vss substrate contacts EE613 VLSI Design

  29. Physical Design – Sea-of-Gate (NAND3) a b c z z a b c a b c EE613 VLSI Design

  30. Physical Design – CMOS Layout Guidelines • Run VDD and VSS in metal at the top and bottom of the cell • Run a vertical poly line for each gate input • Order the poly gate signals to allow the maximal connection between transistors via abutting source-drain connection. • Place n-gate segments close to VSS and p-gate segments close to VDD • Connection to complete the logic gate should be made in poly, metal, or, where appropriate, in diffusion EE613 VLSI Design

  31. Physical Design – Improvement in Density • Better use of routing layers – routes can occurs over cells • More “merged” source-drain connections • More usage of “white” space in sparse gates • Use of optimum device sizes – the use of smaller devices leads to smaller layouts EE613 VLSI Design

  32. Physical Design – Layout Optimization Vdd clk F A<0> F A<1> A<2> A<3> Vss clk A<2> A<1> A<0> A<3> EE613 VLSI Design

  33. Physical Design – Layout Optimization Vdd Wrong Z Right Vss A B C D A B C D EE613 VLSI Design

  34. Physical Design – Transmission Gate EE613 VLSI Design

  35. Physical Design – Transmission Gate EE613 VLSI Design

  36. Physical Design – 2-Input Multiplexer z c a z b z -c a b c c -c EE613 VLSI Design

  37. CMOS Logic – Pseudo-nMOS Logic for EE613 VLSI Design

  38. CMOS Logic – Dynamic CMOS Logic EE613 VLSI Design

  39. If for example then this voltage would be VDD/2 CMOS Logic – Dynamic CMOS Logic EE613 VLSI Design

  40. CMOS Logic – Dynamic CMOS Logic EE613 VLSI Design

  41. CMOS Logic – Clocked CMOS Logic EE613 VLSI Design

  42. CMOS Logic – Pass-Transistor Logic Complementary Single-polarity Cross-coupled EE613 VLSI Design

  43. CMOS Logic – CMOS Domino Logic Basic gate EE613 VLSI Design

  44. CMOS Logic – CMOS Domino Logic Static version Latched version EE613 VLSI Design

  45. CMOS Logic – CMOS Domino Logic EE613 VLSI Design

  46. CMOS Logic – NP Domino Logic EE613 VLSI Design

  47. CMOS Logic–Advantages of Dynamic Logic • Smaller area than fully static gates • Smaller parasitic capacitance, hence higher speed • Glitch free operation if designed carefully EE613 VLSI Design

  48. CMOS Logic – CVSL Basic version A particular function EE613 VLSI Design

  49. (abcd)=(0000) CMOS Logic – CVSL Clocked version A 4-way XOR gate EE613 VLSI Design

  50. Clocking Strategies – Clocked Systems Combinational Logic A simple finite state machine EE613 VLSI Design

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