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C++TESK-SystemVerilog united approach to simulation-based verification of hardware designs

C++TESK-SystemVerilog united approach to simulation-based verification of hardware designs. Mikhail Chupilko Institute for System Programming of RAS http://hardware.ispras.ru. Outline. Hardware verification activities SystemVerilog C++TESK Case study Conclusion.

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C++TESK-SystemVerilog united approach to simulation-based verification of hardware designs

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  1. C++TESK-SystemVerilog united approach to simulation-based verification of hardware designs Mikhail Chupilko Institute for System Programming of RAS http://hardware.ispras.ru

  2. Outline • Hardware verification activities • SystemVerilog • C++TESK • Case study • Conclusion

  3. Hardware Verification Activities • Requirement analysis • Specification refinement • Simple constraint-random based testing • Complicated functional FSM-based testing • Found errors correcting • Test coverage estimating

  4. SystemVerilog Tests Development • SystemVerilog provides powerful means widely used for hardware verification purpose • Several verification technologies like OVM • Closer to verification engineers than C++ • There is no special pipeline-oriented FSM-based methodology

  5. C++TESK Short Description • Developed approach • Open source C++ library • Successor of CTESK – useful toolkit for software verification by means of formal models • Contribution: FSM traverser, reaction ordering checking, different abstraction levels, merging of a set of test systems

  6. Approach: The Common View

  7. Stimuli Generator • Random-based generation • FSM-based generation Current state function State DUV’s Model Stimuli list

  8. Reaction Checker

  9. Case Study

  10. Conclusion • The approach provides additional verification functionality • Quick start with a CDV and reuse of reference models for complicated FSM-based stimuli generation

  11. Thank you

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