1 / 17

Pertemuan 5 Fabrikasi IC CMOS

Pertemuan 5 Fabrikasi IC CMOS. Matakuliah : H0362/Very Large Scale Integrated Circuits Tahun : 2005 Versi : versi/01. Learning Outcomes. Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menyebutkan proses fabrikasiIC CMOS. IC Fabrication.

cole
Télécharger la présentation

Pertemuan 5 Fabrikasi IC CMOS

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Pertemuan 5Fabrikasi IC CMOS Matakuliah : H0362/Very Large Scale Integrated Circuits Tahun : 2005 Versi : versi/01

  2. Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menyebutkan proses fabrikasiIC CMOS.

  3. IC Fabrication Sumber: http://mems.cawru.edu/shortcourse/figure/I_2.1.gif

  4. Diameter Silicon wafer Wafer Die sites Sumber: http://www.amd.com Silicon Processing 2

  5. Silicon oxide O2 flow XSi SiO2 layer Xox Silicon wafer Silicon wafer SiO2 molecues Final structure Growth phase CVD oxide Substrate Material Growth & Deposition

  6. Ion implanter Ion source accelerator Magnetic mass separator Ion beam wafer Silicon nuclei electron cloud Ion Silicon wafer x 0 IC Layers

  7. poly substrate poly After CMP After oxide deposition substrate Glass Pattern on underside Lythography

  8. Photoresist spray Spinning wafer Photoresist coating Resist application Vcuum chuck Coated wafer Edge bead Edge bead Flat resist Wafer Beading Lythography

  9. UV Exposure step Reticle Projection optics (not shown) Reticle shadow Resist-coated Wafer surface Lythography

  10. UV Reticle Resist Wafer Exposure pattern Hardened resist layer Wafer After development and rinsing Lythography

  11. Hardened resist layer Oxide layer Substrate Initial patterning of resist Pattern oxide layer Substrate After etching process Lythography

  12. Arsenic ions Substrate Incoming ion beam n+ n+ Substrate Doped n-type region Lythography

  13. FOX FOX FOX FOX p-epitaxial layer n-well p+ substrate p, Na e. Field oxide growth a. Starting wafer with epitaxial layer n-well p, Na n-well b. Creation of n-well in p-epitaxial layer p, Na Nitride f. Surface preparation n-well n-well p, Na p, Na c. Active area definition using nitride / oxide d. Silicon etch CMOS Process Flow

  14. n-well p, Na a. Gate oxide growth poly n-well p, Na Arsenic implant • Gate oxide growthPoly gate deposition • & patterning resist Boron implant n-well p, Na n+ implant resist d. nSelect mask and implant n-well p, Na c. pSelect mask and implant p+ implant CMOS Process Flow

  15. n-well p, Na W W W W W W Ke pin IC wire a. After anneal and CVD oxide Overglass c. Metal 1 coating and patterning Bond n-well p, Na Metal bonding pad Metal 1 Bonding pad b. After CVD oxide active contact, W plugs n-well p, Na CMOS Process Flow

  16. poly wp Sp-p poly wp Wp = minimum width of polysilicon line Sp-p = minimum poly-topoly spacing Design Rules

  17. RESUME • IC Fabrication: Flow of process. • Silicon Processing: wafer, material growth, deposition. • Lythography: pattern, photoresist coating, exposure steps, etching, n-type. • CMOS Process flow. • Design rules

More Related