Gianluigi De Geronimo , Jack Fried, Shaorui Li, Jessica Metcalfe *

1. VMM1 An ASIC for Micropattern Detectors Gianluigi De Geronimo , Jack Fried, Shaorui Li, Jessica Metcalfe* Neena Nambiar, Emerson Vernon, and Venetios Polychronakos Brookhaven National Laboratory - *CERN TWEPP - September 2012

2. VMM ASIC family VMM: ASIC family for ATLAS Muon Spectrometer upgrade (Micromegas and Thin Gap Chamber) • VMM1: architecture and issues • VMM2: plans VMM1 AR

3. Architecture neighbor direct timing (ToT or TtP) logic or real time address (ART) CA shaper peak mux amplitude time mux mux timing addr mux address 64 channels logic • dual polarity, adj. gain (0.5, 1, 3, 9 mV/fC) (0.11 to 2 pC), adj. peaktime (25-200 ns) • discriminator with sub-hysteresis and neighboring (channel and chip) • address of first event in real time at dedicated output (ART) • direct timing outputs: time-over-threshold or time-to-peak • peak detector, time detector <1 ns • multiplexing with sparse readout and smart token passing (channel and chip) • threshold and pulse generators, analog monitors, channel mask, temperature sensor, 600mV BGR, 600mV LVDS • power 4.5 mW/ch, size 6 x 8.4 mm², process IBM CMOS 130nm 1.2V CA

4. Dual polarity charge amplifier sn 1 N sn Ibias CF CF·N sp Qin Qout = Qin ·N from sensor to virtual ground -∞ -∞ sn sp rail-to-rail output Ibias 1 N sp ESD protection- issue: excessive leakage (few nA) VA

5. Front-end voltage amplifier L = 180 nm W = 10 mm M = 200 ID = 2 mA Vin MI inverting output stage with bootstrapping Mc2bias circuit MC1 MS2 MS2 VC2 MC2 comp Vout C MC2 VC2 MS1 fast response to positive charge switchable compensation - issue: unstable when set for large caps SC

6. Gain and energy resolution Gain vs input capacitance ENC vs input capacitance difference due to increased peaking time high drop due to failing switchable compensation disagreement part due leakage from ESD protection, part being investigated analog dynamic range Qmax/ENC exceeds 12,000 DR

7. Delayed Dissipative Feedback (DFF) Delay feedback of dissipative element (i.e. resistor RS) Q·N CS RS CF CS V1 Q·N CF·N Vout -∞ -∞ other poles Q charge gain N shaper DDF shaper higher analog dynamic range Applies also to the other stages of the shaper see G. De Geronimo and S. Li, TNS 58, Oct. 2011 DS

8. Sub-hysteresis discrimination Comparator input stage output upper threshold upper threshold hysteresis lower threshold • Positive feedback • high speed at low Vi+-Vi- • hysteresis set NMOS ratio hysteresis sets minimum detectable Sub hysteresis 1 - set window lower • limit reduced to overlap • no action on input • or threshold signals 2 - raise window after trigger switch NMOS ratio hold until triggers back PD

9. Peak measurements Large amplitude Small amplitude • with sub-hysteresis • nominal hysteresis 20 mV • ~3 mV offset • from external buffers TD

10. Timing measurements Uses peak-found signal • low time-walk • high timing resolution • sub-ns timing • ns time walk (can be calibrated) disagreement with theor. due to effective peaktime G. De Geronimo, in “Medical Imaging” by Iniewski TM

11. Direct timing Direct timing ToT and TtP • dedicated output for each channel • available as ToT or TtP (time-to-peak) OM

12. Amplitude measurements Linearity Channel uniformity • within 2% for ~ 1 V full swing • peak dispersion includes baseline • threshold dispersion 8.8 mV rms • requires improved matching and/or larger • trimming range (currently 15 mV) FN

13. ART and Neighboring Two chips (a,b) and one channel exceeding threshold (64 in chip a) • ART • threshold or peak • with address flags and readout multiplexed sequential peak detect outputs • analog pulses • only one exceeds threshold • neighbors (chan. and chip) enabled for peak detection V2

14. Plans for VMM2 trigger neighbor direct timing (ToT, TtP, PDAD) logic or real time address (ART) 6bPDAD timing clock mux CA shaper peak 10b ADC mux mux 10b ADC time FIFO data (ampl., time, addr.) 6b coarse mux addr. channel count logic data clock • fixes, higher gain setting, lower gain setting (5pC) • external trigger • 6-bit peak detector and digitizer (PDAD) for direct timing • 10-bit 5MS/s ADCs per channel and FIFO • fully digital IOs, derandomization, simultaneous measurement and readout • 6-bit counter for coarse timing

15. Conclusions • VMM is an ASIC family for the ATLAS Muon Spectrometer upgrade (Micromegas, TGC) • VMM1 has been developed and tested, with results in good agreement with the design • Main issues with the charge amplifier compensation (limits the rise time at large capacitance) and the large leakage from the ESD protection • VMM2 (in design) will integrate a number of improvements for simultaneous measurement and readout Acknowledgment Ken A. Johns, Sarah L. Jones (University of Arizona, USA) Nachman Lupu (Technion Haifa, Israel) Howard Gordon and Craig Woody (BNL, USA) ATLAS review team (J. Oliver, M. Newcomer, R. Richter, P. Farthouat)

16. Backup slides

17. Peak detection 1 - Track (< threshold) • Analog output is tracked at hold capacitor • MP and MN are both enabled 2 - Peak-detect (> threshold) • Pulse is tracked and peak is held • Only MP is enabled • Comparator is used as peak-found 3 - Read (at peak-found) • Amplifier re-configured as buffer • High drive capability • Amplifier offsets is canceled • Enables rail-to-rail operation • Accurate timing • Some pile-up rejection

18. ENC and timing coefficients for various shapers G. De Geronimo, in “Medical Imaging” by Iniewski