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Chapter 9 Finite-State Machines

Finite-state machine background Writing VHDL for a FSM FSM initialization FSM flipflop output signal FSM synthesis Exercise. Chapter 9 Finite-State Machines. Slides 2-9 based on: Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis. Introduction.

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Chapter 9 Finite-State Machines

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  1. Finite-state machine background Writing VHDL for a FSM FSM initialization FSM flipflop output signal FSM synthesis Exercise Chapter 9 Finite-State Machines Slides 2-9 based on: Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis EE514

  2. Introduction • Describing embedded system’s processing behavior • Can be extremely difficult • Complexity increasing with increasing IC capacity • Past: washing machines, small games, etc. Hundreds of lines of code • Today: TV set-top boxes, Cell phone, etc. Hundreds of thousands of lines of code • Desired behavior often not fully understood in beginning • Many implementation bugs due to description mistakes/omissions • English (or other natural language) common starting point • Precise description difficult to impossible • Example: Motor Vehicle Code – thousands of pages long... EE514

  3. An example of trying to be precise in English • California Vehicle Code • Right-of-way of crosswalks • (b) The provisions of this section shall not relieve a pedestrian from the duty of using due care for his or her safety. No pedestrian shall suddenly leave a curb or other place of safety and walk or run into the path of a vehicle which is so close as to constitute an immediate hazard. No pedestrian shall unnecessarily stop or delay traffic while in a marked or unmarked crosswalk. • 21950. (a) The driver of a vehicle shall yield the right-of-way to a pedestrian crossing the roadway within any marked crosswalk or within any unmarked crosswalk at an intersection, except as otherwise provided in this chapter. • (c) The provisions of subdivision (b) shall not relieve a driver of a vehicle from the duty of exercising due care for the safety of any pedestrian within any marked crosswalk or within any unmarked crosswalk at an intersection. • All that just for crossing the street (and there’s much more)! • How can we (precisely) capture behavior? EE514

  4. Partial English description System interface “Move the elevator either up or down to reach the requested floor. Once at the requested floor, open the door for at least 10 seconds, and keep it open until the requested floor changes. Ensure the door is never open while moving. Don’t change directions unless there are no higher requests when moving up or no lower requests when moving down…” up Unit Control down open floor req Request Resolver buttons inside elevator b1 b2 ... bN up1 up/down buttons on each floor up2 dn2 up3 dn3 ... dnN Introductory example: An elevator controller • Simple elevator controller • Request Resolver resolves various floor requests into single requested floor • Unit Control moves elevator to this requested floor EE514

  5. Finite-state machine (FSM) model • Trying to capture this behavior as sequential program is a bit awkward • Instead, we might consider an FSM model, describing the system as: • Possible states • E.g., Idle, GoingUp, GoingDn, DoorOpen • Possible transitions from one state to another based on input • E.g., req > floor • Actions that occur in each state • E.g., In the GoingUp state, u,d,o,t = 1,0,0,0 (up = 1, down, open, and timer_start = 0) • Try it... EE514

  6. req > floor u,d,o, t = 1,0,0,0 GoingUp !(req > floor) timer < 10 req > floor !(timer < 10) u,d,o,t = 0,0,1,0 UnitControl process using a state machine Idle DoorOpen u,d,o,t = 0,0,1,1 req == floor req < floor !(req<floor) u,d,o,t = 0,1,0,0 GoingDn u is up, d is down, o is open req < floor t is timer_start Finite-state machine (FSM) model EE514

  7. Formal definition • An FSM is a 6-tuple F<S, I, O, F, H, s0> • S is a set of all states {s0, s1, …, sl} • I is a set of inputs {i0, i1, …, im} • O is a set of outputs {o0, o1, …, on} • F is a next-state function (S x I→ S) • H is an output function (S → O) • s0is an initial state • Moore-type • Associates outputs with states (as given above, H maps S → O) • Mealy-type • Associates outputs with transitions (H maps S x I→ O) • Shorthand notations to simplify descriptions • Implicitly assign 0 to all unassigned outputs in a state • Implicitly AND every transition condition with clock edge (FSM is synchronous) EE514

  8. Formal definition EE514

  9. req > floor u,d,o, t = 1,0,0,0 GoingUp !(req > floor) timer < 10 req > floor u,d,o,t = 0,0,1,0 !(timer < 10) Idle DoorOpen u,d,o,t = 0,0,1,1 req == floor req < floor !(req<floor) u,d,o,t = 0,1,0,0 GoingDn req < floor Describing a system as a finite state machine 1. List all possible states • 2. For each state, list possible transitions, with conditions, to other states • 3. For each state and/or transition, list associated actions • 4. For each state, ensure exclusive and complete exiting transition conditions • No two exiting conditions can be true at same time • Otherwise nondeterministic state machine • One condition must be true at any given time • Reducing explicit transitions should be avoided when first learning u is up, d is down, o is open t is timer_start EE514

  10. Writing VHDL for a FSM Consider FSM transition diagram EE514

  11. Writing VHDL for a FSM Use case statement to describe the combinational circuit and a clock sensitive process to infer flip-flops use IEEE.std_logic_1164.all; entity RWCNTL is port( CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic); end RWCNTL; architecture RTL of RWCNTL is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; begin comb : process (CURRENT_STATE, START, RW, LAST) begin DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; EE514

  12. Writing VHDL for a FSM case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then NEXT_STATE <= READING; else NEXT_STATE <= WAITING; end if; when WRITING => WRSIG <= '1'; EE514

  13. Writing VHDL for a FSM if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; NEXT_STATE <= IDLE; end case; end process; seq : process begin wait until CLOCK'event and CLOCK = '1'; CURRENT_STATE <= NEXT_STATE; end process; end RTL; EE514

  14. Writing VHDL for a FSM EE514

  15. Writing VHDL for a FSM EE514

  16. Performance of FSM Similar to regular sequential circuit EE514

  17. Sample timing diagram EE514

  18. State assignment • State assignment: assign binary representations to symbolic states • In a synchronous FSM • All assignments work • Good assignment reduce the complexity of next-state/output logic • Typical assignment • Binary, Gray, one-hot, almost one-hot EE514

  19. State assignment EE514

  20. FSM initialization To asynchronously reset FSM add if statement which includes elseif with rising edge of the clock library IEEE; use IEEE.std_logic_1164.all; entity RWCNTLR is port( RESETn : in std_logic; CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic); end RWCNTLR; architecture RTL of RWCNTLR is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; begin comb : process(CURRENT_STATE, START, RW, LAST) begin DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; EE514

  21. FSM initialization case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then NEXT_STATE <= READING; else NEXT_STATE <= WAITING; end if; when WRITING => WRSIG <= '1'; if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; NEXT_STATE <= IDLE; end case; end process; seq : process (CLOCK, RESETn) begin if (RESETn = '0') then CURRENT_STATE <= IDLE; elsif (CLOCK'event and CLOCK = '1') then CURRENT_STATE <= NEXT_STATE; end if; end process; end RTL; EE514

  22. FSM initialization EE514

  23. FSM initialization To infer a synchronous reset use if statement before case statement in the combinational part library IEEE; use IEEE.std_logic_1164.all; entity RWCNTLR1 is port( RESETn : in std_logic; CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic); end RWCNTLR1; architecture RTL of RWCNTLR1 is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; begin comb : process(RESETn, CURRENT_STATE, START, RW, LAST) begin DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; if (RESETn = '0') then NEXT_STATE <= IDLE; else EE514

  24. FSM initialization case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then NEXT_STATE <= READING; else NEXT_STATE <= WAITING; end if; when WRITING => WRSIG <= '1'; if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; NEXT_STATE <= IDLE; end case; end if; end process; seq : process (CLOCK, RESETn) begin if (RESETn = '0') then CURRENT_STATE <= IDLE; elsif (CLOCK'event and CLOCK = '1') then CURRENT_STATE <= NEXT_STATE; end if; end process; end RTL; EE514

  25. FSM initialization EE514

  26. FSM flip-flop output signal To have outputs driven by flip-flops use output signal assignment in the process under rising edge of the clock library IEEE; use IEEE.std_logic_1164.all; entity RWCNTLRF is port( RESETn : in std_logic; CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic); end RWCNTLRF; architecture RTL of RWCNTLRF is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; signal DONE_comb, RDSIG_comb, WRSIG_comb : std_logic; begin comb : process(CURRENT_STATE, START, RW, LAST) begin DONE_comb <= '0'; RDSIG_comb <= '0'; WRSIG_comb <= '0'; EE514

  27. FSM flip-flop output signal case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG_comb <= '1'; if LAST = '0' then NEXT_STATE <= READING; else NEXT_STATE <= WAITING; end if; when WRITING => WRSIG_comb <= '1'; if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE_comb <= '1'; NEXT_STATE <= IDLE; end case; end process; seq : process (CLOCK, RESETn) begin if (RESETn = '0') then CURRENT_STATE <= IDLE; DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; elsif (CLOCK'event and CLOCK = '1') then CURRENT_STATE <= NEXT_STATE; DONE <= DONE_comb; EE514

  28. FSM flipflop output signal Note that synthesized circuit has 3 more latches RDSIG <= RDSIG_comb; WRSIG <= WRSIG_comb; end if; end process; end RTL; EE514

  29. Comparing to the original design the output signals are latched at the next clock edge Note that synthesized circuit has 3 more latches EE514

  30. FSM flipflop output signal This code can be simplified if the case statement is included inside if statement in the seq process temporary signals are avoided and simulation runs faster architecture COMBINED of RWCNTLRF is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE : STATE_TYPE; begin seq : process (CLOCK, RESETn) begin if (RESETn = '0') then CURRENT_STATE <= IDLE; DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; elsif (CLOCK'event and CLOCK = '1') then DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; EE514

  31. FSM flipflop output signal case CURRENT_STATE is when IDLE => if START = '0' then CURRENT_STATE <= IDLE; elsif RW = '1' then CURRENT_STATE <= READING; else CURRENT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then CURRENT_STATE <= READING; else CURRENT_STATE <= WAITING; end if; when WRITING => WRSIG <= '1'; if LAST = '0' then CURRENT_STATE <= WRITING; else CURRENT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; CURRENT_STATE <= IDLE; end case; end if; end process; end COMBINED; EE514

  32. FSM synthesis • Some synthesis tools can synthesize the FSMs. • They usually generate better results than a general synthesis from VHDL code. • It is better for an FSM to be an independent block (VHDL code). • This makes the synthesis process easier, especially in writing synthesis constraints, encoding states, and synthesis commands. EE514

  33. To Create a State Diagram • Select New Source on the Project menu. • Select State Diagram from the list in the dialog box. • Enter a name for the new state diagram. • Enter a directory in which the state diagram will reside. • Click Next. • Click Finish. The StateCAD program displays. • Select Design Wizard on the File menu in StateCAD. Click Save File • Click the Generate HDL button. • Close StateCAD. • Click Add Source on the Project menu to add the state diagram .dia file and the HDL module to your ISE project. EE514

  34. FSM EE514

  35. FSM EE514

  36. FSM EE514

  37. Synthesized FSM -- -- File: D:\FDNTN\ACTIVE\PROJECTS\FSM\fsm1.vhd -- created: 10/25/99 23:08:10 -- from: 'D:\FDNTN\ACTIVE\PROJECTS\FSM\fsm1.asf' -- by fsm2hdl - version: 2.0.1.52 -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library SYNOPSYS; use SYNOPSYS.attributes.all; entity fsm1 is port (clock: in STD_LOGIC; last: in STD_LOGIC; rw: in STD_LOGIC; start: in STD_LOGIC; done: out STD_LOGIC; rdsig: out STD_LOGIC; wrsig: out STD_LOGIC); end; architecture fsm1_arch of fsm1 is -- SYMBOLIC ENCODED state machine: Sreg0 type Sreg0_type is (idle, reading, waiting, writing); signal Sreg0: Sreg0_type; begin --concurrent signal assignments --diagram ACTIONS; Sreg0_machine: process (clock) begin if clock'event and clock = '1' then case Sreg0 is when idle => if rw='0' then Sreg0 <= writing; elsif start='0' then Sreg0 <= idle; elsif rw='1' then Sreg0 <= reading; end if; when reading => if last='0' then Sreg0 <= reading; elsif last='1' then Sreg0 <= waiting; end if; EE514

  38. Synthesized FSM when waiting => Sreg0 <= idle; when writing => if last='0' then Sreg0 <= writing; elsif last='1' then Sreg0 <= waiting; end if; when others => null; end case; end if; end process; -- signal assignment statements for combinatorial outputs rdsig_assignment: rdsig <= '1' when (Sreg0 = reading and last='0') else '1' when (Sreg0 = reading and last='1') else '1'; done_assignment: done <= '1' when (Sreg0 = waiting) else '1'; wrsig_assignment: wrsig <= '1' when (Sreg0 = writing and last='0') else '1' when (Sreg0 = writing and last='1') else '1'; end fsm1_arch; EE514

  39. StateCAD • Translates state diagrams to HDL based designs • Automatically analyzes designs for problems such as • Stuck-at states • Conflicting state assignments • Indeterminate conditions • Includes StateBench EE514

  40. StateCAD • Support concurrent state machines • Graphical operators for states • Mealy & Moore outputs • Resets • Combinatorial and synchronous logic • Text comments EE514

  41. FSM Wizard in StateCAD EE514

  42. Logic Wizard in StateCAD • StateCAD Logic Wizard for data flow structures • Shifters, registers,latches, counters, muxes, etc. • Requires object type, attributes, and signal names • Handles boolean equations within the wizard EE514

  43. Overview • StateCAD diagrams have .dia extensions • File names have an eight character limit • StateCAD output • Language specific files • VHDL, Verilog, or ABEL • VHDL and Verilog output files can be compiled using various tools • Exemplar • Synopsys EE514

  44. Beginning a Diagram • Project  New Source • State Diagram • File Name EE514

  45. Adding States • In the Draw Mode tool bar, use the State Mode command • States are given unique names when they are added or copied • May be used as actual state names • Can be changed or edited • Syntax of states: NAME OUTPUTS=1; NAME_ONLY EE514

  46. Outputs • Output list contains equations • Output equations • State variables • Outputs support complex data flow logic • Bit or vector equations • Counters • Muxes • Example: NAME CNTR <= CNTR + 1; BUSOUT = (sigA OR sigB) AND NOT(sigC OR sigD) EE514

  47. Outputs • Output Wizard is the easiest way to add outputs • In Edit State (double-click on a state), select the Output Wizard button EE514

  48. Transitions • Use the Transition button to draw curved and straight transitions: • Straight transitions: Click on one state, then click on another state • Curved transitions: Click on one state (a small square appears), another small square will follow the cursor (click to place), one more square will appear, place the final square on the state destination EE514

  49. Curved Transitions • Multiple segment transitions • Enable through Options menu  Graphics • Deselect “Single Segment Curve” • Unlimited number of segments • Each segment contains a starting point, two control points, and an endpoint EE514

  50. Transition Conditions • To add a transition condition, double-click on the transition for the Edit Condition dialog box • Conditions are Boolean equations • Syntax errors and indeterminate conditions are checked during compilation • Conditions may use inputs, outputs, and logic variables • State names and variables from one machine may be used in the condition of another machine. This allows communication between state machines EE514

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