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EE4271 VLSI Design

EE4271 VLSI Design. Logic Synthesis. Logic Synthesis. Starts from RTL description in HDL or Boolean expressions Outputs a standard cell netlist. Boolean Function. f: B m Y n B = {‘0’, ‘1’}, Y = {‘0’, ‘1’, ‘-’} The function is incompletely specified, don’t care ‘-’

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EE4271 VLSI Design

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  1. EE4271 VLSI Design Logic Synthesis EE 4271 VLSI Design

  2. Logic Synthesis • Starts from RTL description in HDL or Boolean expressions • Outputs a standard cell netlist EE 4271 VLSI Design

  3. Boolean Function • f: Bm Yn • B = {‘0’, ‘1’}, Y = {‘0’, ‘1’, ‘-’} • The function is incompletely specified, don’t care ‘-’ • For each output, space of Bm can be partitioned into • on-set: all inputs leading to output ‘1’ • off-set: all inputs leading to output ‘0’ • dc-set: all inputs leading to output ‘-’ EE 4271 VLSI Design

  4. Points in Input Space • Assigning ‘1’ or ‘0’ to each of the m Boolean variables x1, x2, …, xm specifies a point in input space Bm • Example • (‘1’, ‘0’, ‘1’) in B3 • x1=‘1’ Λ x2=‘0’ Λ x3=‘1’ • x1•x2•x3 EE 4271 VLSI Design

  5. Terminology • Literal: a Boolean variable or its complement • Minterm: a product of all input variables or their complements – a point in Bm • Cube: a product of input variables or their complements • The fewer number of variables, the bigger space covered EE 4271 VLSI Design

  6. Boolean Function Representation • A Boolean function can be specified by a sum of minterms • The expression has a minterm for each point in the on-set EE 4271 VLSI Design

  7. Implicant and Cover • An implicant is a cube whose points are either in the on-set or the dc-set • A prime implicant is an implicant that is not included in any other implicant • A set of prime implicants that together cover all points in the on-set (and some or all points of the dc-set) is called a prime cover EE 4271 VLSI Design

  8. Irredundant Cover • An prime cover is irredundant when none of its prime implicants can be removed from the cover • An irredundant prime cover is minimal when the cover has the minimal number of prime implicants EE 4271 VLSI Design

  9. Goal of Logic Synthesis • Find a minimum irredundant prime cover • An irredundant prime cover is not necessarily a minimum EE 4271 VLSI Design

  10. Quine-McCluskey Algorithm • Calculate all prime implicants of the union of the on-set and dc-set, omitting prime implicants that only cover points of dc-set • Finds the minimum cost cover of all minterms in the on-set by the obtained prime implicants EE 4271 VLSI Design

  11. Set Covering Problem • Given a universe U={e1, …, en}, a collection of subsets {S1, …, Sm} where each subset contains some elements in universe • cost wi is associated with each subset Si • find a subcollection C (cover) such that C covers the entire universe • Famous NP-complete problem • On-set U, a prime implicant an S EE 4271 VLSI Design

  12. Example of Set Cover • U={1,2,3,4} • S1={1,2}, w=2 • S2={1,3,4}, w=3 • S3={3}, w=1 • S4={2,4}, w=2 • S5={2,3}, w=2 • S6={1,2,4}, w=3 • C={S3,S6} is the optimal solution • S3 is redundant in C={S1,S2,S3} , and C={S1,S2} is not optimal EE 4271 VLSI Design

  13. Greedy Algorithm • C = empty [the cover] • E= empty [record elements which have been covered] • While there is uncovered element • Find the subset Si which is most cost effective, that is, the Si with smallest w(Si)/|Si-E|. [weight of subset over the elements in the subset but not covered so far] • For each e in Si-E, set price(e)=w(Si)/|Si-E| • Put all e in Si to E • Put Si in the current partial cover C EE 4271 VLSI Design

  14. Running Example (Iter 1) • U={1,2,3,4} • S1={1,2}, w=10 • S2={1,3,4}, w=9 • S3={3}, w=7 • S4={2,4}, w=4 • S5={2,3}, w=2 • Iteration 1, E = empty • w(S1)/|S1-E|=10/2=5 • w(S2)/|S2-E|=9/3=3 • w(S3)/|S3-E|=7/1=7 • w(S4)/|S4-E|=4/2=2 • w(S5)/|S5-E|=2/2=1 • Pick S5 • E = {2,3} • C = {S5} EE 4271 VLSI Design

  15. Running Example (Iter 2) • U={1,2,3,4} • S1={1,2}, w=10 • S2={1,3,4}, w=9 • S3={3}, w=7 • S4={2,4}, w=4 • S5={2,3}, w=2 • Iteration 2, E={2,3}, C = {S5} • w(S1)/|S1-E|=10/1=10 • w(S2)/|S2-E|=9/2=4.5 • w(S3)/|S3-E|=7/0=+infty • w(S4)/|S4-E|=4/1=4 • Pick S4 • E = {2,3,4} • C = {S5,S4} EE 4271 VLSI Design

  16. Running Example (Iter 3) • U={1,2,3,4} • S1={1,2}, w=10 • S2={1,3,4}, w=9 • S3={3}, w=7 • S4={2,4}, w=4 • S5={2,3}, w=2 • Iteration 3, E={2,3,4}, C={S5,S4} • w(S1)/|S1-E|=10/1=10 • w(S2)/|S2-E|=9/1=9 • w(S3)/|S3-E|=7/0=+infty • Pick S2 • E = {2,3,4,1} • C = {S5,S4,S2} EE 4271 VLSI Design

  17. The Other Example • n elements and a collection of m=n+1 subsets • U={1,2,…n} • S1={1}, w(S1)=1/n • S2={2}, w(S2)=1/(n-1) • S3={3}, w(S3)=1/(n-2) • … • Sn={n}, w(Sn)=1 • Sn+1={1,2,…,n}, w(Sn+1)=1.0001 • Our solution {S1,S2,…,Sn}, weight = ln n • Optimal solution {Sn+1}, weight = 1.0001 EE 4271 VLSI Design

  18. Summary Logic synthesis Primary implicant Minimum cost irredundant prime cover Set Cover Greedy Algorithm EE 4271 VLSI Design 18

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