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Multicycle Datapath 9 October 2013

CDA 3101 Fall 2013 Introduction to Computer Organization. Multicycle Datapath 9 October 2013. Review. Construction of the Datapath Determine instruction types R-format Conditional Branch Unconditional Branch Load/store

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Multicycle Datapath 9 October 2013

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  1. CDA 3101 Fall 2013Introduction to Computer Organization Multicycle Datapath 9 October 2013

  2. Review • Construction of the Datapath • Determine instruction types • R-format • Conditional Branch • Unconditional Branch • Load/store • Develop datapath modules (RF, ALU, Memory, SignExt) • Connect modules to form composite datapath • Single-Cycle Datapath • All instructions take one cycle (CPI = 1)  • Cycle time dictated by circuit settling time • All operations take time of slowest operation (load)

  3. Overview – Multicycle Datapath • Each instruction has multiple stages • Each stage takes one cycle • Instruction fetch • Instruction decode / Data fetch • ALU ops / R-format execution • R-format completion • Memory access completion Each stage can re-use hardware from previous stage More efficient use of hardware and time >>New Hardware required to buffer stage output >>New Muxes required for hardware re-use >>Expanded Control for new hardware All instructions use these

  4. Recall: Simple Datapath Data Instruction memory rd Data memory rs Address Registers PC ALU Address rt Instruction +4 Data imm Opcode, funct Controller • Datapath is based on register transfers required to execute instructions • Control causes the right transfers to happen

  5. Recall: R-format Datapath ALU op Register File 3 Read Reg 1 Read Reg 2 Write Register Write Data Read Data 1 Read Data 2 Instruction ALU Register Write • Format:opcoder3, r1, r2 Zero Result

  6. Recall: Load/Store Datapath Fetch DecodeExecute

  7. Recall: Branch Datapath Fetch DecodeExecute

  8. Hi-Level View: Multicycle DP Buffer Registers Instr. Fetch Instr. Decode/Data Fetch Execute

  9. Hi-Level View: Multicycle DP How do we make multicycle datapath (DP)??? • Replace3 ALUs from the single-cycle DP with one ALU • Addone multiplexer to select ALU input • Addone control line for the ALU input multiplexer • New inputs: Constant = 4 [PC + 4] • Sign-ext., shifted offset [BTA calc.] • Addtemporary (buffer) registers: (storage betw.cycles) • MDR: Memory Data Register • IR: Instruction Register • A,B: ALU operand registers • ALUout: ALU output register

  10. Multicycle DP:The Full Monty

  11. Multicycle DP: 1-bit Ctl. Signals

  12. Multicycle DP: 2-bit Ctl. Signals

  13. Making Sense of Multicycle DP Step 1: Decompose the MC/DP execution sequence into cycles Step 2: Examine which cycles apply to which instructions One-Cycle Steps R-fmt lw sw beq j • Instruction Fetch • Instruction Decode / Data Fetch • ALU ops / R-format Execution • R-format Completion • Memory Access Completion

  14. Multicycle DP: R-format Step 1: Fetch instr. // Store in IR // Compute PC + 4 Step 2: Decode instruction: opcode, rd, rs, rt, funct fields Data fetch: Apply rs, rt to Register File Data Read into A,B buffer registers (ALUin) Step 3: ALU operation (ALUsrcA, ALUsrcB, ALUop) ALU output goes into ALUout register Step 4: ALUout register contents written to Register File write input Register number in rd written (Assert: RegWrite,RegDst) CPI for R-format = 4 cycles

  15. Multicycle DP: Store Word (sw) Step 1: Fetch instr. // Store in IR // Compute PC + 4 Step 2: Decode instruction: opcode, rs, rt, offset fields Data fetch: Apply rt to Register File => Base address Data Read into A buffer register (Base) SignExt,Shift offset field into B buffer register Step 3: ALU operation (ALUsrcB, ALUop) => Base + Offset ALU output goes into ALUout register Step 4: ALUout register contents applied as Memory Address Assert: MemWrite [ALUout => RegFile] CPI for Store = 4 cycles

  16. Multicycle DP: Load Word (lw) Step 1: Fetch instr. // Store in IR // Compute PC + 4 Step 2: Decode instruction: opcode, rd, rt, offset fields Data fetch: Apply rt to Register File => Base address Data Read into A buffer register (Base) SignExt,Shift offset field into B buffer register Step 3: ALU operation (ALUsrcB, ALUop) => Base + Offset ALU output goes into ALUout register Step 4: ALUout register contents applied as Memory Address Assert: MemRead Step 5: Memory Data Out routed to Register File write input Register number from rd written to (Assert: CPI for Load = 5 cycles

  17. Multicycle DP: Cond. Branch Step 1: Fetch instr. // Store in IR // Compute PC + 4 Step 2: Decode instruction: opcode, rs, rt, offset fields Data fetch: Apply rs, rt to Register File BTA calc: SignExt,Shift offset field into B buffer register ALU compose PC, offset => BTA Step 3: ALU operation (ALUsrcA, ALUsrcB, ALUop) = compare ALU output present at Zero register causes Control to select BTA or PC+4 CPI for Conditional Branch = 3 cycles

  18. Multicycle DP: Jump Step 1: Fetch instr. // Store in IR // Compute PC + 4 Step 2: Decode instruction: opcode, address fields JTA calc: SignExt,Shift offset field [Bits 27-0] Concatenate with PC [Bits 31-28] => JTA Step 3: PC replaced by the Jump Target Address (JTA) PCsource = 10, PCWrite asserted CPI for Jump = 3 cycles

  19. Conclusions • MIPS ISA: Three instruction formats (R,I,J) • One cycle per stage, Different stages per format • One-Cycle StepsR-fmt lw sw beq j • Instruction Fetch • Instruction Decode / Data Fetch • ALU ops / R-format Execution • R-format Completion • Memory Access Completion Challenge: More involved control design

  20. Almost Here: Pipelining 

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