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DSPs for Future Wireless Base-Stations

DSPs for Future Wireless Base-Stations. Sridhar Rajagopal and Joseph R. Cavallaro May 8, 2000. This work is supported by Texas Instruments, Nokia, Texas Advanced Technology Program and NSF. Outline. Background DSP Implementation and Task Partitioning Reduced Complexity Algorithms

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DSPs for Future Wireless Base-Stations

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  1. DSPs for Future Wireless Base-Stations Sridhar Rajagopal and Joseph R. Cavallaro May 8, 2000 This work is supported by Texas Instruments, Nokia, Texas Advanced Technology Program and NSF

  2. Outline • Background • DSP Implementation and Task Partitioning • Reduced Complexity Algorithms • VLSI Architecture • Extensions for DSPs

  3. Evolution of Wireless Communications First Generation Voice Second/Current Generation Voice + Low-rate Data (9.6Kbps) Third Generation + Voice + High-rate Data (2 Mbps) + Multimedia W-CDMA

  4. Noise +MAI Base Station Reflected Paths Direct Path User 1 User 2 Communication SystemUplink

  5. Main Processing Blocks Decoding Channel Estimation Detection Baseband Layer of Base-Station Receiver

  6. C67 at 166MHz; Spreading Code = 31 Current DSP Implementation

  7. Reasons for Poor Performance • Sophisticated, Compute-Intensive Algorithms • Need more MIPs/FLOPs performance • Unable to fully exploit pipelining or parallelism • Bit - level computations / Storage • Task Partitioning • Multiple DSPs, FPGAs

  8. Iterative Scheme for Estimation • Tracking • Method of Gradient Descent • Stable convergence behavior • Symmetric, Positive Definite Rbb • Condition number - MAI, SNR, Preamble length • µ - reciprocal of maximum eigenvalue

  9. Comparison of Bit Error Rates (BER) -1 10 -2 BER 10 O(K2N) MF ActMF ML ActML O(K3+K2N) -3 10 4 5 6 7 8 9 10 11 12 Signal to Noise Ratio (SNR) Simulations - AWGN Channel MF – Matched Filter ML- Maximum Likelihood ACT – using inversion

  10. 0 10 MF - Static MF - Tracking ML - Static ML - Tracking -1 10 BER -2 10 -3 10 4 5 6 7 8 9 10 11 12 SNR Fading Channel with Tracking Doppler = 10 Hz, 1000 Bits,15 users, 3 Paths

  11. VLSI Implementation • Channel Estimation as a Case Study • Area - Time Efficient Architecture • Real - Time Implementation • Minimum Area Overhead • Bit- Level Computations - FPGAs • Core Operations - DSPs

  12. Area-Time Tradeoffs • Area-Constrained Architecture • Pico-cells ; lower data rates • Time-Constrained Architecture • Maximum achieve-able data rates • Area-Time Efficient Architecture • Real-Time with minimum area overhead

  13. Characteristics of Wireless Algorithms • Massive Parallelism • Bit-level Computations • Matrix Based Operations • Memory Intensive • Complex-valued Data • Approximate Computations

  14. Instruction Set Extensions • To accelerate Bit level computations in Wireless • Integer - Bit Multiplications • Multiuser Detection, Decoding, Cross Correlation • Bit - Bit Multiplications • Auto-Correlation, Channel Estimation • Useful in other Signal Processing applications • Speech, Video,,,

  15. 64-bit Register A 64-bit Register B 8 8 + + x 8 64-bit Register C SIMD Parallelism

  16. 64-bit Register D[i][j] 8 8 +/- +/- 8 8-bit Control Register b[i] 64-bit Register D[i][j] Integer - Bit Multiplications 64-bit Register C[j] For i = 1..8, j= 1..8 D[i][j] = D[i][j] + b[i]*C[j] (Cross-Correlation)

  17. Computational Savings • Avoid bit multiplications and control structures • 4 8-bit Multiply • Latency 3 • 8 8-bit Add • Latency 1 • Cross-Correlation Example • 64 multiply, 64 add

  18. Conclusions • Architecture and Algorithms to meet real-time • Task Decomposition • Real Time with Multiple Processing Elements • Iterative Algorithms • Reduce Complexity, Simpler Implementation • VLSI Implementation • Real-Time with minimum Area Overhead • Extensions to DSPs for acceleration

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