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Computer Architecture

Computer Architecture. CS423: Lecture 12 Dynamic Scheduling Jahangir Ikram. COMPARISON . FP PIPELINE VS SCOREBOARD. Revision. EX. IF. ID. A 1. A 2. A 3. A 4. Mem. WB. M 1. M 2. M 7. Divide. Multiple Cycle Floating Point Pipeline. Register File. Scoreboard of CDC 6600.

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Computer Architecture

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  1. Computer Architecture CS423: Lecture 12 Dynamic Scheduling Jahangir Ikram

  2. COMPARISON • FP PIPELINE VS SCOREBOARD

  3. Revision

  4. EX IF ID A 1 A 2 A 3 A 4 Mem WB M 1 M 2 .. M 7 Divide Multiple Cycle Floating Point Pipeline

  5. Register File Scoreboard of CDC 6600 EX Mem Read Operands Read Operands WB EX ISSUE Read Operands A 1 A 2 A 3 A 4 Register File M 1 M 2 .. M 7 Read Operands Read Operands Divide Check for WAR Check for RAW, Read Values from Register File when free Check for WAW, FU

  6. Ask students to fill this and compare with 2 slides before

  7. Data Hazards • RAW Hazard ADD.D F3, F1, F2 SUB.D F5, F6, F3 • WAW Hazard DIV.D F3, F1, F2 SUB.D F3, F6, F5 • WAR Hazard DIV.D F3, F1, F2 SUB.D F5, F6, F3 ADD.D F3, F6, F7

  8. TRUE and False Dependencies Find Dependencies in this code • DIV.D F0,F2,F4 • ADD.D F6,F0,F8 • S.D F6,0(R1) • SUB.D F8,F10,F14 • MUL.D F6,F10,F8

  9. WAR and WAW Data Dependencies • DIV.D F0,F2,F4 • ADD.D F6,F0,F8 • S.D F6,0(R1) • SUB.D F8,F10,F14 • MUL.D F6,F10,F8

  10. Name Dependencies • WAW and WAR dependencies are also called name dependencies: they do not carry a value between two instructions • Can be removed by avoiding use of the same name: rename the destination register whenever a new value is created • Both compiler (statically) and processor (dynamically) can do that

  11. Register Renaming: Compiler • DIV.D F0,F2,F4 • ADD.D F6,F0,F8 • S.D F6,0(R1) • SUB.D F20,F10,F14 • MUL.D F21,F10,F20 • Only RAW or struc. hazards left

  12. Dynamic Register Renaming • Use some architecture invisible registers for renaming, called rename registers to avoid WAW. • Read and keep a copy of available operands at the time of issue, this will avoid WAR. The values are stored in reservation station.

  13. Tomasulo’s Algorithm LD/ST Wait for Operands Wait for Operands EX TAC Mem Access Mem Access DATA Register FILE Tag Integer Integer Wait for Operands Wait for Operands Wait for Operands EX CDB CDB ISSUE/ Rename to RS ISSUE/ Rename to RS FP FP ADD Wait for Operands Wait for Operands Wait for Operands A 1 A 1 A 2 A 2 A 3 A 3 A 4 A 4 Register FILE Check for RS Wait for Operands Wait for Operands Wait for Operands M 1 M 1 M 2 M 2 .. .. M 7 M 7 Wait for Operands Wait for Operands Wait for Operands Divide Divide Check for RAW

  14. MIPS FP Unit Using Tomasulo’s Algorithm From Instruction Unit FP registers Instruction Queue Load / Store Unit FP Operations Operand Busses Address unit Stop Buffers Reservation Stations Address Data FP multipliers Memory unit FP Adders Common Data Bus (CDB)

  15. Structure of Reservation Station • Qj,Qk: Like scoreboard • Vj, Vk: Contains values of two operands. Value are valid if Qj and Qk is zero • Busy • OpCode • A: For Target address TA or Imm value • Registers have Qi field as before

  16. Tomasulo’s Example

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