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NSS-MIC 2009 Summary

NSS-MIC 2009 Summary. Rafael Ballabriga PH-ESE-ME. NSS Conference. Photodetectors and Scintillation detectors Semiconductor Detectors Analog and digital circuits Nuclear measurements and monitoring techniques New detector concepts and instrumentation Instrumentation for homeland securit y

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NSS-MIC 2009 Summary

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  1. NSS-MIC 2009 Summary Rafael Ballabriga PH-ESE-ME

  2. NSS Conference Photodetectors and Scintillation detectors Semiconductor Detectors Analog and digital circuits Nuclear measurements and monitoring techniques New detector concepts and instrumentation Instrumentation for homeland security Data acquisition and analysis systems Radiation damage effects Computing and software for experiments Trigger and front-end systems Gaseous detectors High energy physics instrumentation Gamma ray imaging Neutron Imaging Accelerators and beam line instrumentation

  3. MIC Conference X-Ray imaging PET/SPECT instrumentation Simulation and modelling of medical imaging systems Animal imaging and instrumentation techniques Image processing and evaluation Image reconstruction Quantitative imaging techniques

  4. This talk • ASICS • PX90DC (P. Grybos, AGH UST Cracow) • Medipix3 (R. Ballabriga, CERN) • ASIC for SDD-based X-ray Spectrometers (G. De Geronimo, BNL) • New dynamic TOT method (K. Shimazoe, Tokio University) • 3D Interconnects • 3D IC @ Fermilab (G. Deptuch, Fermilab) • New techniques in SOI pixel detectors (Y. Arai, KEK) • MAPS based on 3D integration (W. Dulinski, IPHC Strasbourg) • SiPM • 2 posters/~250 in NSS-2006 • 15 posters/~250 in NSS-2009 (and a few talks) • Introduction • SPIROC chip (W. Shen, Heidelberg) • BASIC chip (C. Marzocca, Politecnico di Bari and INFN) • Readout of SiPM for TOF PET (P. Jarron, CERN) • Summary

  5. ASICs

  6. PX90DC (P. Grybos) Prototype readout chip for hybrid pixel detector Functionaliy: Single Photon Counting, Energy window, continuous readout 90nm CMOS technology (TSMC) 9 metal layers 40x32 pixels 100umx100um pixel

  7. PX90DC (P. Grybos)

  8. Characterization of the Medipix3 Pixel Readout Chip R. Ballabriga, M.Campbell, E. H. M. Heijne, J. Jakubek, X. Llopart, R. Plackett, S. Pospisil, L. Tlustos, Z. Vykydal, W.Wong CERN, PH department

  9. Medipix3 Introduction Medipix3 is a Hybrid Pixel Detector readout chip working in Single Photon Counting Mode Designed in 130nm CMOS technology Highly configurable pixel Flexible readout scheme (ROI, Configurable output port width) It implements a novel architecture for improving the system’s spectrometric performance Eliminating the distortion from charge diffusion in the spectrum

  10. Charge summing and allocation concept The winner takes all • Charge is summed in every 4 pixel cluster on an event-by-event basis • The incoming quantum is assigned as a single hit 55µm

  11. Medipix3 Pixel Schematic

  12. Design in 130 nm CMOS technology, 8 metal layers ~1600 transistors per pixel Pixel Layout • 1. Preamplifier • 2. Shaper • 3. Two discriminators with 5-bit threshold adjustment • 4. Pixel memory (13-bits) • 5. Arbitration logic for charge allocation • 6. Control logic • 7. Configurable counter 55 µm 55 µm

  13. Medipix3 chip Pixel matrix of 256 x 256 pixels Bottom periphery contains: LVDS drivers and receivers Band-Gap and 25 DACs (10 9-bit and 15 8-bit) 32 e-fuse bits EoC and 2 Test pulse generators per pixel column Temperature sensor Full IO logic and command decoder Power/Ground pads TSV landing pads Pads extenders Top periphery contains: Power/Ground pads TSV landing pads Pads extenders > 115 Million transistors Typical power consumption: 600 mW in Single pixel mode 900 mW in Charge summing mode 17.3 mm 14.1 mm

  14. Medipix3 Modes of Operation

  15. Electrical Measurements

  16. Threshold scan with a 109Cd source (preliminary) Threshold scan with a 109Cd source (Shutter time 2.5s) 2 peaks expected (~22kev and ~25kev)

  17. Threshold scan with a 109Cd source (preliminary) Threshold scan with a 109Cd source (Shutter time 2.5s)

  18. Threshold scan with a 109Cd source (preliminary) Threshold scan with a 109Cd source (Shutter time 2.5s)

  19. Measured X-ray tube spectrum (preliminary) Spectrum of a W X-ray tube at 50kV and I=10mA. ~2mm Al prefiltering. Ni foil filtering. (8.3keV K-edge) 0.5s exposure time

  20. Summary of electrical measurements The chip can be operated up to 460Mrad and beyond

  21. Silicon Drift Detector

  22. Asic for SDD-based X-ray Spectrometers (G. De Geronimo) Gain 2.6 and 5.2V/fC (0.83V/ke-) 5th order shaper 16 channels (1700 x 200 µm2/ch) 2mW/channel Analog and leakage current monitors Temp sensor

  23. Asic for SDD-based X-ray Spectrometers (G. De Geronimo)

  24. Asic for SDD-based X-ray Spectrometers (G. De Geronimo)

  25. A New Dynamic Time over Threshold Method K. Shimazoe1, H. Takahashi1, T. Fujiwara2, T. Furumiya3, J. Ohi3, Y. Kumazawa3 1Bioengineering, The University of Tokyo, Tokyo,Bunkyo-ku, Japan2Nuclear Engineering and Management, The University of Tokyo, Tokyo,Bunkyo-ku, Japan3Shimadzu Corporation, Kyoto, Japan

  26. A New Dynamic Time Over Threshold Method (K. Shimazoe) • Time Over Threshold (TOT) system has advantage over pulse height measurements on its high integrity and low power dissipation because of its binary readout and circuit simplicity. However the relation between TOT and input charge is strongly nonlinear and dynamic range is limited. We propose a new dynamic TOT system which converts the pulse height to pulse width with a dynamically changing threshold. This kind of TOT system can enable wider dynamic range and improves linearity since the threshold follows the input signal and even shorten the width of TOT pulse. We show the concept of dynamic TOT system and results with discrete circuits. It can improve the dynamic range and theoretically it is possible to desired relation between TOT and input charge by using dedicated threshold function. We also designed and fabricated 48 channel dynamic TOT ASIC with 0.25um TSMC CMOS technology.

  27. A New Dynamic Time Over Threshold Method (K. Shimazoe)

  28. 3D interconnects

  29. Vertically Integrated Circuits at Fermilab (G. Deptuch)

  30. Vertically Integrated Circuits at Fermilab (G. Deptuch)

  31. 3D integrated circuits • Benefits • Density • Optimized processing (specialized layers e.g. analog/digital) • Speed (reducing interconnects distance) • Challenges • Bonding (need high yields to be competitive) • Packaging (thin wafers) • Main customers • Stacked microprocessors and SRAM devices

  32. 3D integrated circuits (vendors)

  33. Vertically Integrated Circuits at Fermilab (G. Deptuch) VIP1/VIP2 chips. (Vertically integrated pixel) 3 tiers: Data sparsification, Time stamp, Analog Time stamping pixel readout chip for ILC

  34. Vertically Integrated Circuits at Fermilab (G. Deptuch) VIPIC CHIP (Vertically integrated photon imaging chip) (Light Sources) How it works: X-ray Photon Correlation Spectroscopy (XPCS) is a technique that is used at X-ray light sources to generate speckle patterns for the study of thedynamics in various equilibrium and non-equilibrium processes The chip is divided in 16 group of 256 pixels read out in parallel but through separate LVDS serial ports Data sparsification is performed in each group Sensors fabricated at BNL; DBI bonding done at Ziptronix (all inprocess)

  35. New techniques in SOI pixel detectors (Y. Arai) 0.2um Silicon on insulator CMOS technology. Slide: Y. Arai (Oct. 15, 2009@CLIC09)

  36. New techniques in SOI pixel detectors (Y. Arai) Slide: Y. Arai (Oct. 15, 2009@CLIC09)

  37. Ultra Thin, Fully depleted MAPS based on 3D integration of Heterogeneous CMOS layers (Wojciech Dulinski, Strasbourg)

  38. Ultra Thin, Fully depleted MAPS based on 3D integration of Heterogeneous CMOS layers (Wojciech Dulinski) • Aim: Fast, High precision radiation tolerant and ultrathin CMOS sensors • Solution: MAPS on fully depleted epitaxial substrate with first stage buffer amplifier on the same wafer and 3D coupling to the readout electronics • Requirements: • Fast readout frame ~10us • Pixel pitch ~20um • Ultrathin ~50-100um • 5uW/pixel, ENC ~12 e- rms, Gain ~150uV/e-

  39. Ultra Thin, Fully depleted MAPS based on 3D integration of Heterogeneous CMOS layers (Wojciech Dulinski) NSS: XFAB 0.35um Slide : W. Dulinski EUDET-JRA1 Meeting, Strasbourg, March 2009

  40. SiPM

  41. A SiPM is a matrix of Single Photon Avalanche Diodes (SPADs) with a common output. A SPAD is build as a PIPN junction diode in series with a quench resistance. It is biased over the breakdown voltage. SiPM principle i(t) The output of the SiPM is the sum of all the SPADs 90mA 60mA 30mA t François Powolny

  42. SiPM François Powolny

  43. SPIROC ASIC (Wei Shen)

  44. SPIROC ASIC (Wei Shen) 1MIP~16 pixels fired Threshold ½ MIP Jitter<500ps

  45. SPIROC ASIC (Wei Shen)

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