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Timing and Event System S. Allison, M. Browne, B. Dalesio, J. Dusatko, R. Fuller, A. Gromme, D. Kotturi, P. Krejcik, S. Norum, D. Rogind, H. Shoaee, M. Zelazny. Outline. Overview – HW and Reqts Hardware Test Stand Long-Haul Fiber Issues and Plans Outstanding Software Issues and Tasks

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  1. Timing and Event SystemS. Allison, M. Browne, B. Dalesio, J. Dusatko, R. Fuller, A. Gromme, D. Kotturi, P. Krejcik, S. Norum, D. Rogind, H. Shoaee, M. Zelazny

  2. Outline • Overview – HW and Reqts • Hardware Test Stand • Long-Haul Fiber Issues and Plans • Outstanding Software Issues and Tasks • Wish List

  3. Hardware Block Diagram 2007 Commissioning Modulator Triggers Existing Control System Beam Path Acq and Calibration Triggers PADs and PACs BPM FEE Acc and Standby Triggers Timing Crate E V G F A N 1 F A N 2 P N E T I O C EVR EVR 1 EVR 2 EVR 3 I O C I O C 360Hz Fiducial RF Timing BPM Crates LLRF Crate 119MHz Clock Future MPS Beam Rate, Beam Path Fiber Distribution: Timing Pattern, Timestamp, Event Codes Triggers Triggers TORO FEE Trigger EVR 1 C A M 1 C A M 2 I O C 1 … EVR 4 C A M 7 C A M 8 I O C 4 F A N 3 EVR 1 C A M 1 I O C 1 ... EVR 8 C A M 8 I O C 8 EVR F A N 4 I O C Profile Monitor Crate Laser Steering Crate Toro Farc Crate … …

  4. Event Generator (EVG-200) SLAC PNET Receiver Micro-Research Finland Oy Receives the MPG broadcast sent to SLC micros and passes it to the EVG • SFP transceiver • Optical signal to EVRs (fan-outs) • RF input • Event clock • divided from RF • /1*,/4, ... /12 EVR Fan Out module Line syncronisation input 360 Hz *SLAC addition

  5. Micro-Research Finland Oy • Programmable outputs • 5(3) TTL level • 2 LVPECL level • External trigger input • SFP transceiver • Optical signal from EVG (or fan-out) Recovered RF output Event Receiver – PMC version Event Receiver (EVR-200-RF)

  6. Modifications to EVG • 119MHz clock input • In the absence of a ÷1 input, a daughterboard was made containing a clock receiver IC to allow us to input 119MHz directly • EVG AC-line input • 360Hz fiducial input was rerouted with firmware change to avoid addition of jitter from internal 10 kHz clock and phase shifter

  7. Tallies for 2007, Plans for Next Phase • # EVRs = 31 installed (mostly PMC) • Add 60 more EVRs - 34 VME, 26 PMC • # IOCs with EVRs = 28 • Add 40 more IOCs with EVRs • # EVR Fanouts = 4 • Add 5 more fanouts (1 every 200m) • # Hardware Triggers = 120+ • All TTL except 2 NIM triggers for QDCs • Most require short cables (except LLRF) • Add ? more

  8. Timing Requirements

  9. Event System Requirements • Event Generator IOC: • Send out proper event codes at 360Hz based on: • PNET pattern input (beam code and bits that define beam path and other conditions) • Add LCLS conditions such as BPM calibration on off-beam pulses , diagnostic pulse etc. • Future – event codes also based on new MPS and user input • Send out system timestamp with encoded pulse ID from PNET • Send out PNET pattern to be used by SLC-aware IOCs • Manage user-defined beam-synchronous acquisition measurement definitions (event definition or EDEF) • Check for match between user EDEFs and input PNET pattern at 360Hz and tag matches in outgoing pattern

  10. Event System Requirements, cont • Event Receiver IOC: • Set trigger delays, pulse widths, and enable/disable via user requests (not yet done on a pulse-by-pulse basis) • Set event code per trigger (triggering done in HW when event code received) • Receive event pattern 8.3 msec before corresponding pulse • Perform beam-synchronous acquisition based on tags set by EVG in the event pattern • Perform beam-synchronous acquisition for the SLC-aware IOC based on the PNET part of the event pattern • Process pre-defined records when specific event codes are received (not yet available – bug!)

  11. EVG Event Time Line – 4 Fiducials 360Hz Fiducial F3 (n=3) F1 (n=1) F2 (n=2) F0 (n=0) 2.8 5.6 Time (msec) 0 9.3 8.3 1.0 R3 HW starts sending event codes, starting with fiducial event code R2 R1 R0 Receive Fn+3 PNET, determine Fn+3 LCLS pattern, and advance pipeline (n-2->n-1->n) P3 P0 P2 P1 L2 L3 L0 L1 Send LCLS pattern Set Event Codes in Other RAM based on the last patterns for Fn+1 E3 E4 E1 E2 B-3 120Hz BEAM B0

  12. Trigger Event Time Line – 1 Beam Pulse (B0) Record processing (event, interrupt) Hardware Triggers Receive pattern for 3 pulses ahead Triggering Event Codes Start Beam Kly Standby Event Timestamp, pattern records, and BSA ready Acq Trigger Kly Accel Fiducial Event Received Fiducial B0 F3 18 500 0 1023 Time (usec) 100 0.3

  13. Trigger Control Display

  14. EVG Displays

  15. Hardware Test Stand EVR Output (Trigger Signal) Delay between fid to trigger: Minimum intrinsic system delay + adjustable value EVG Input (360Hz fiducial)

  16. Timing Jitter Test Results Agilent 54845A EVR jitter w.r.t. fiducial PDU jitter w.r.t. fiducial 30 min. 13 ps rms jitter 13 ps rms jitter

  17. Event System HW: Long-Haul Dist. • For the next phase, the biggest challenge is Long-Haul distribution of timing data via the Fiber-Optical (F-O) Links • Why? • MRF Event System is designed around Multi-Mode SFP (Small Form-Factor Pluggable) F-O links which allow a maximum fiber length of ~300 meters • Our requirements include runs of several Kilometers (at least) • Cannot daisy-chain the event F-O links: exceeds the jitter budget • Temperature effects on long fibers – drift, but how bad?

  18. Event System HW: Long-Haul Dist. • Proposed Solution: New HW and some testing • Single-Mode, pin-compatible SFP modules are commercially available (Agilent ACFT-57R5) • All us to go ~10KM • Should plug right into our event system HW • Still does not solve temperature-induced phase-drift problem • Propose to solve by either/and: • Running Long Fiber in temperature-controlled environment • Re-Syncing EVRs to a locally-distributed 119MHz source • Long-haul fiber test: • Function of Single-Mode SFP Modules • Drift, Trigger time jitter, Phase Noise

  19. Event System – Long-Haul Fiber System Test

  20. Issues and Tasks • Outstanding problem (presumably software) where CPU hangs when EVR interrupts are enabled. Some IOCs running without interrupts (hardware triggers but without timestamps, BSA, or event code IRQs). • Outstanding bug with IRQ processing on VME EVRs • Software not yet in place to handle hardware and communication errors. • Changing an event code for a specific trigger requires a change in the delay to trigger at the same time – need database to automate the change • Need generic timing delay scan software that works for most device types • Need to get status of RF clock into the system (external interface) • Ability to change trigger attributes on a pulse-by-pulse basis using simple conditional expressions

  21. Wish List • When 2 event codes trigger a device on the same pulse, the second event restarts the delay. Wish the second event would be ignored instead. • Interrupt from the EVG on fiducial trigger (AC line trigger)

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