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Next-generation Chips & Computing with Atoms

Next-generation Chips & Computing with Atoms. Igor Markov ACAL / EECS, Univ. of Michigan. Why EDA? (Electronic Design Automation). Key motivations for Computer Engineering Designing & building faster, cheaper, more efficient computers and comm. systems Developing new applications

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Next-generation Chips & Computing with Atoms

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  1. Next-generation Chips &Computing with Atoms Igor Markov ACAL / EECS, Univ. of Michigan

  2. Why EDA?(Electronic Design Automation) • Key motivations for Computer Engineering • Designing & building faster, cheaper, more efficient computers and comm. systems • Developing new applications • Traditional disciplines in CE • Computer Architecture(von Neumann orthodoxy, long pipelines, etc) • VLSI (design on a grid, standard blocks) • Typical approach • “write RTL, run through CAD tools, tape out” • is insufficient for large, leading-edge chips

  3. Technology trends undermine traditional approach • CPU speed is not increasing anymore • Massive parallelism required (10,000s multiplications in one cycle ?) • Delay is dominated by interconnect • When writing RTL, neither delaynor power are captured explicitly • Buffering required, gate sizing very helpful • It is very difficult to write good RTL • Designs must be automatically optimized • Older CAD tools choke on recent chips • Synthesis, layout, verification are NP-hard++,but tools have to work on 20M-gate chips • New interconnect structures (FPGAs)

  4. Market trends undermine traditional approach • Many semiconductor companiescompete on cost and time-to-market • E.g., standard-compliant chips (WiFi, USB, PCI-X) • Increasing impact of embedded software • Hardware prototypes must be available early to software developers • Most of the design-cycle is spent running tools for design and verification • Great opportunity for new, fast EDA algorithms • C, SystemC  gates • Intellectual Property (IP) reuse required(placement with large fixed-size blocks still unsolved)

  5. Thinking outside the box • Placing macro blocks simultaneouslywith millions of small gates • Resisted by community & industry until 2002 • Adopted quickly when benefits were demonstrated • Register retiming • Can significantly improve delay • Resisted by designers (too big a change) • Resisted by companies (too risky) • Adopted after verification tools caught up • Automatic bit-width reduction • On path to adoption • Automatic resource sharing (many types)

  6. … really outside the box Atomic-scale quantum-mechanical behavior • A bit can store 0 and 1 at the same time! • But when you look at it, it randomly decidesto assume one of those values!!! • Some circuits can process all possible input combinations at the same time! • But you can only see some of the results!!!

  7. Quantum WeirdnessCan Be Useful • Quantum computers (in theory)can break the RSA cryptosystem • NMR systems at IBM & MIT • Ion traps built by Prof. Chris Monroe at Physics • Quantum secure channels are already runningin Washington and Boston (in telecom fiber) • A quantum satellite communication system(single-photons) developed at Los Alamos • We are studying the design and simulationof quantum circuits • Recent work: a theory of quantum MUXes,algorithms for synthesis of quantum logic circuits

  8. Our Group • A broad range of research opportunities • Electronic Design Automation: “computers making computers”(significant HW, SW and AI components) • Novel chip types and design optimizations • Verification • Computational support for “Extreme VLSI” • Computational miracles (AI and Theory comp.) • 7 graduate students • Two currently at IBM Research in Austin, TX • One at Mentor Graphics in San Jose, CA • Recent graduates • IBM Research in NY (TJ Watson) • Synopsys Advanced Technology group

  9. Our Group Contact email: imarkov@umich.edu • Required skill set • Strong analytical abilities • Design and implementation of algorithms • Logic circuits • Software development (for EDA projects) • Strong math. background (for quantum projects) • Our work is used in industry softwareto design and verify industrial chips • Publications, conference travel • CA, TX, Europe, Asia • Several best paper awards • First places at ICCAD CADathlon • Finding jobs after Ph.D. or M.S. is easy

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