http://socdsp.ee.nchu.edu.tw

1. nLint 操作教學 http://socdsp.ee.nchu.edu.tw

2. 在終端機下 Step1:#source /usr/cad/spring_soft/CIC/debussy.cshrc Step2:#nLint -gui

3. Select rule(1)

4. Select rule(2) 選擇所需rules

5. nLint rule(1) • Simulation • Combinational Loop • Infinite Loop • Signal in Sensitivity List Changed in the Block • Loss of Significant Bit • Synthesis • Logic Expression Used in Sensitivity • Delay in Non-blocking Assignment • Blocking/Non-blocking Assignment in Edge-triggered Block • Inferred Latch • ERC • Floating Net • Partial Input Floating • Output Floating • Input Floating • DFT • Gated Clock • Buffered Clock • Reset Driven by Combinational Logic

6. nLint rule(2) • Design Style • Two-process Style Not Used for FSM • Clock Driven by Sequential Logic • Clock Signal Used on Both Edges • No Set or Reset Signal • No Glue Logic Allowed in Top Module • Language Construct • Bit Width Mismatch in Assignment • Multi-bit Expression when One Bit Expression is Expected • Bit Range Specified for Parameter • Bit Width Mismatch Between Module Port and Instance Port • HDL Translation • Verilog/VHDL Reserved Words • Include Compiler Directive Used • Naming Convention • Port Name Too Long • Clock Name Prefix or Suffix • Active Low Signal Name Prefix or Suffix • Port Name Does Not Follow the Connected Signal

7. nLint rule(3) • Coding Style • Line Too Long • TAB Used in Indentation • More than One Statement per Line • Unconventional Port Declaration Order • VITAL Compliant • For VHDL only • Clock • Generated Reset • Generated Clock • Tri-state Buffer in a Clock Path • Block Interconnect • Conflict of Hierarchy Interconnection • Block Assembly Error in the Same Hierarchy Level • reference - /uer/cad/spring_soft/verdi/2006.04v1/nLint/doc/pdf/rule.pdf

8. Save your rule file

9. step1 step2 step3

10. step1 step2 Step3:Select your file Step4:add your select file

11. Run nLint Run nLint Check your coding style

13. Use .f file run nLint Prepare data 要檢查的RTL code

14. Use .f file run nLint Source debussy.cshrc Run nLint by .f file

15. Use .f file run nLint Link check