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MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-0

MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-03-01 : 2010-12-31). WP1: Giuliana Gangemi WP2: Andr é Juge WP3: Wilmar Heuvelman WP4: Fabio Campi WP5: Loris Vendrame Coordinator: Jan van Gerwen

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MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3 Review period: m13 : m22 (2010-0

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  1. MODERN 2010 Review ENIAC-120003 MODERNRef. Technical Annex MODERN_PartB Rev2 v3.3Review period: m13 : m22 (2010-03-01 : 2010-12-31) WP1: Giuliana Gangemi WP2: André Juge WP3: Wilmar Heuvelman WP4: Fabio Campi WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: March 1st, 2010

  2. Agenda (1) • General information (Jan) • Objectives • Consortium • Relationship between workpackages • Gantt Chart • Resources planned and used • Overview of deliverables and milestones status • Cooperation, dissemination and exploitation • Project management: progress, funding problems and amendments • Other issues, Q&A • For WP1 (Giuliana), WP2 (André), WP3 (Wilmar) and WP4 (Fabio) • Relationship between workpackages • Progress, highlights and lowlights • Matrices showing ‘Domain and Technology Overview per Task and Partner’ • Link withother WPs and Tasks • Technical status and achievements of deliverables (incl. changes) • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  3. Agenda (2) • For WP5 (Loris) • Relationship between workpackages • Progress, highlights and lowlights • Technical status and achievements of deliverables (incl. changes) • Structuring of demonstrators: goals and objectives • Link withother WPs and Tasks • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  4. Specifically, the main goals of the project are: • Advanced, yet accurate, models of process variations for nanometre devices, circuits and complex architectures. • Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. • Reliability, noise, EMC/EMI. • Timing, power and yield. • Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels. • Validation of the modelling and design methods and tools on a variety of silicon demonstrators. Layout and strain induced variability (Synopsys) Objectives • The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. MODERN 2010 Review March 1st, 2011

  5. Consortium • The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe. MODERN 2010 Review March 1st, 2011

  6. Relationship between workpackages MODERN 2010 Review March 1st, 2011

  7. Gantt Chart (1) MODERN 2010 Review March 1st, 2011

  8. Gantt Chart (2) MODERN 2010 Review March 1st, 2011

  9. Resources planned and used MODERN 2010 Review March 1st, 2011

  10. Overview of deliverables and milestones status (1)Deliverables MODERN 2010 Review March 1st, 2011

  11. Overview of deliverables and milestones status (2)Milestones Conclusion: All Deliverables and Milestones due before 31-12-2010 (M22) are ready M24 Deliverablesand Milestones are on schedule MODERN 2010 Review March 1st, 2011

  12. Website Public section Restricted section MODERN 2010 Review March 1st, 2011

  13. Cooperation, dissemination and exploitation • A Workshop at DATE 2010 with the theme ‘The Fruits of Variability Research in Europe’ was organized. This workshop was a co-operation of the UK EPSRC project, FP7 STREP project REALITY and MODERN • VARI Workshop, 2010 May 26-27, Montpellier, France • Contribution to the Workshop on Simulation and Characterisation of Statistical CMOS Variability and Reliability was presented, Sept. 9th 2010, Bologna, Italy • MODERN participated in the Poster & Demo Session at European Nanoelectronics Forum 2010 in Madrid, Spain • Large number of publications • Main meetings: • General meetings in Catania (Nov. 9&10, 2010) attended by 30+ persons present and 10+ called in • Due to the travel restrictions that many companies/institutes still face most of the interaction between partners is by phone and email MODERN 2010 Review March 1st, 2011

  14. Project management: progress, funding problems and amendments • Progress: All planned deliverables ready • Most uncertainties in countries causing funding and (national) administrative issuese.g. Italy, Swiss, Spain and Austria are resolved • Amendments: • The change of project coordinator from ST to NXP and ST-Crolles being replaced by ST-Grenoble • The removal of some inconsistencies between some deliverables • The subcontracting of work by Glasgow to GSS Ltd. • CSEM withdraws due to lack of national funding as of 29-06-2010 • To account for the leaving of some NXP employees and a related change in direction of the NXP PDM group the deliverables D5.3.2 and D5.3.3 are (slightly) changed • To account for some technical difficulties encountered in the research activities within ST-I Tasks 3.1, 3.4 and 5.3 are (slightly) changed • Coming: partner #6 Infineon Technologies Austria AG is included in the transaction between Infineon and Intel MODERN 2010 Review March 1st, 2011

  15. Other issues Q&A • Italy ? • Payment to Spanish partner ? MODERN 2010 Review March 1st, 2011

  16. WP1 agenda Introduction Progress, highlights and lowlights Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 Link with other WPs and Tasks Cooperation Other issues, Q&A MODERN 2010 Review March 1st, 2011

  17. Introduction: Progress, highlights and lowlights PERIOD UNDER REVIEW 1. Clearly define the issues related to nano-electronic technologies that will be tackled in the MODERN project (e.g.,sensitivity of performances, power, yield, deficiencies of existing design techniques, etc). 2. Set the target technologies for which the above listed problems will be faced. 3. Define the specifications of the prototype tools, methods and flows that will come up as solutions of the previously listed problems. 4. Define the requirements of the integration work needed to embed the new tools into the existing design frameworks provided by the EDA partners within the flows in use at ST, NMX, IFX,THL, AMS and NXP. 5. Define up front all activities of all WPs of MODERN exception made of the management. HIGHLIGHT : Activities recovered past delay D1.3 released OCT 2010 M1.1Problem definition and Tests M1.4 user guides M1.2 Integraton specs MODERN 2010 Review March 1st, 2011

  18. Matrices showing ‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011

  19. Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011

  20. Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011

  21. Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011

  22. Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011

  23. Link with other WPs and Tasks MODERN 2010 Review March 1st, 2011

  24. Collaborations WP leader: ST-I Strong dependence on partners: NMX, NXP,THL,IFX,AMS,ST-I, ST-F Collaboration with partners: NMX, NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F, Telephone conferences with: NMX,NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F according requirements of deliverables ALL SEPT – OCT 2010. With WP Leaders weekly since the month of December MODERN 2010 Review March 1st, 2011

  25. WP2 agenda • Progress, highlights and lowlights • Matrices showing‘Domain and Technology Overview per Task and Partner’ • Link withother WPs and Tasks • Technical status and achievements of deliverables (incl. changes): D2.1.1, D2.2.3, D2.3.2 and D2.5.1 • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  26. WP2 Objectives • Provide a chain of TCAD simulations tools which enable simulation of the impact of process variations and reliability on device level, including compact models and mixed mode device/circuit simulation • Assess the impact of process and device variations for relevant technologies, mainstream planar bulk CMOS down to 45/32nm, new device architectures on bulk & on SOI suitable for 22nm, NVM technologies, and non-silicon technologies • Compare simulation results with hardware and calibrate them on hardware to verify PV methodology and to foster physical understanding of major sources of PV in above technologies • Key-figures: 5 Tasks/18 deliverables (reports): • Process (2) & device (6) simulation • Electricalcharacterization (4) & Reliability(3) • Compact modeling (3) • Coveringboth Tools/Methodologyimprovements and Application results • Widespectrum of technologies & devices applications • 45nm: planarMosfet • 32nm: planarMosfet, FinFet • 22nm: FD SOI Mosfet • State-of-art NVM • Discrete Power Device, SiC, GaN/AlGaN • HV CMOS MODERN 2010 Review March 1st, 2011

  27. WP2 TaskStructure and Contributors MODERN 2010 Review March 1st, 2011 27

  28. WP2 Domain and Technology overview per task and partner • PV awaretools and methods are of commoninterest; they are developped and applied to a widespectrum of technologies (Project book rev2 v2.4.1). • Significantcommunalities of technologytargets, exceptdifferentones for Process and Device simulation. • (not funded) MODERN 2010 Review March 1st, 2011

  29. WP2: Links with other WPs and Tasks WP2 WP3 WP4 T2.1 T3.1 T2.2 T4.1 T3.2 T2.3 IFX T4.2 T3.3 T2.4 LETI T3.4 T4.4 T2.5 WP5 T5.1 T5.2 T5.3 MODERN 2010 Review March 1st, 2011

  30. WP2 Progress, Highlights and Lowlights • Progress: • Project on track. 4 deliverables completed in 2010: D2.1.1, D2.2.3, D2.3.2 and D2.5.1 • Overall 8 deliverables over 18 completedso far • March-Dec 2010 periodhighlights: • Process variations: TCAD method for process compact modeling (PCM) demonstrated in HVMOS and Power MOS technologies (STI, AMS, TUW). • Device simulation: • analysis of dominant variability sources in state of-the-art Non-Volatile-Memory technologies(UNET, UNGL, NMX, SNPS). • Consistency of variabilityestimates over differenttools and methods for NVM devices (UNET, NMX, UNGL, SNPS) • Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (ST-I) • Characterization of 1/f noise dispersion behavior in 45nm bulk CMOS (NXP) • PV-aware circuit-level models for standard CMOS technologies (down to 45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2) , and Non-Volatile-Memory technologies (NMX, UNET) • Lowlights: • 2010: D2.3.2 delayed M18->M21 • 2011: 4 monthsdelayexpected for coming D2.2.4 (consistent 32nm coreCmos data required for D224, D233, and D253) MODERN 2010 Review March 1st, 2011

  31. Task 2.1 PV awareProcess simulation Goal: To perform process simulation including treatment of PV. Application to discrete power devices, SiC, AlGaN/GaN (ST-I) and HV-CMOS technologies (AMS). Task Leader: valeria.cinnera@st.com MODERN 2010 Review March 1st, 2011 31

  32. Partners:ST-I, AMS, TUW Progress: TCAD method for process compact modeling (PCM) demonstrated in Power MOS (STI) and HVMOS technology (AMS, TUW). Aimis to propagateFabequipmenttolerance (1) to Process variations and (2) to Devicelevel, and to determineDevice performances variations in terms of sensitivities, distributions,andyieldestimates TOOL is under construction; a β-release has been created Done for Silicon Power Mos (STI), HV Mosfets (AMS) Running for AlGaN/GaNHemt and SiC diode (STI). TOOL links with : Sentaurus Process (all), Sentaurus Device (STI), Minimos (TUW), PCM studio(all) Next activities: In the final report D2.1.2 (M27) will be also addressed: - an interface between the semiconductor FAB equipment and the process simulation environment, to enable analysis of variations, and yield estimates - an interface between commercial process simulator and Minimos-NT (a two-dimensional device simulator from TUW) - the activity done on a Silicon Power MOS will be extended to compound materials (STI). T2.1 Progress MODERN 2010 Review March 1st, 2011 32

  33. Process recipes Process flow Virtual device High Level factory Specific process conditions TCAD Experiments Mask Layout FAB1 PCM PCM Process Compact model derived from TCAD Technology transferred to FAB2 using PCM FAB2 T2.1 PV aware process simulation (ST-I) MODERN 2010 Review March 1st, 2011 33

  34. PCM approach (STI) PCM STUDIO EHD5 SEMICELL • Synopsys platform: • Sentaurus and PCM Studio • Simulation of Power-Mos semi cell with the nominal values of the process input parameters SENTAURUS WORKBENCH DOE PCM • Parameter screening to identify the process parameters that • have an important impact on target electrical parameters. • Parameterized simulation setup (DOE) generating several simulation runs. • Device simulations of breakdown and I-V characteristic for each experiment. • Extraction of RSM model of device characteristics as function of process parameters using PCM Studio. MODERN 2010 Review March 1st, 2011 34

  35. T2.1 PV aware process simulation(AMS – TUW) • Process Flow Process Parameters Correlation Interface between commercial Synopsys Process Simulator and Minimos Device Simulator Parameter Extraction Sentaurus Work Bench Minimos MODERN 2010 Review March 1st, 2011 35

  36. T2.2 PV awareDevice Simulation Task Leader: a.asenov@elec.gla.ac.uk MODERN 2010 Review March 1st, 2011

  37. Partners:UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS Goal:The focus is on activities: to include variability in device simulation tools to illustrate the tool capabilities in respect of progressively scaled CMOS devices and to validate the simulation capabilities in respect of variability measurements of real devices Progress (achieved): D2.2.1 (M6): A comprehensive review of the necessity for variability TCAD simulation. Review of current industrial practices based on a comprehensive survey. Prioritisation D2.2.2 (M12) Study of 45nm CMOS Stress effects on mobility in SOI and FinFETs Development of Sentaurus and GARAND to include Variability. D2.2.3 (M18): nextslides Comprehensive study of Variability in a 32nm NVM Floating Gate Flash Cell Development and comparison of simulators developed by Partners T2.2 Progress MODERN 2010 Review March 1st, 2011 37

  38. T2.3.3 NVM Template Structure • Analyse the dominant variability sources in state of the art NVM technologies. • NVM cell designed with a 32nm Half Pitch, TCAD supplied by Numonyx. • 32nm channel length, with an area of 64x64nm. • Indicative of 32nm technology but does not represent actual device or process. • Used to investigate the impact of statistical variability on NVM. MODERN 2010 Review March 1st, 2011

  39. T2.2.3: NVM Variability Sources RDD LER LWR OTF PSG ITC MODERN 2010 Review March 1st, 2011

  40. T2.2.3: NVM Variability Sources MODERN 2010 Review March 1st, 2011

  41. T2.2.3: NVM Rounded Gate Flat AA &FG Rounded AA & FG MODERN 2010 Review March 1st, 2011

  42. T2.2 3 simulation toolsenhancements (example) Implementations in Sentaurus Device in the releases 2010.03 and 2010.12 with corresponding applications MODERN 2010 Review March 1st, 2011

  43. Partners:UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS Nextactivities: D2.2.4 (M24->M28) “Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET). Efficient compact model extraction procedures for modeling process variations and device fluctuations (NXP, UNET, POLI)” Some contributions in progress: UNGL Comprehensive simulation of variability in 32nm devices Statistical Compact Model extraction based on above Methodology has been created in D2.2.2 and D2.2.3 for large scale variability simulation Methodology for compact model extraction has been worked out in D2.5.1 IMEP Variability studies using 3D full quantum NEGF simulations of SiNW with the impact of surface roughness and discrete trap charge in gate all around dielectric  Semi-analytical modelling of drain current variability in C32 including dopant induced correlated mobility fluctuations  Influence of pockets in C32 using semi-analytical random dopant model T2.2 PV awareDevice Simulation: nextactivities MODERN 2010 Review March 1st, 2011 43

  44. T2.3 Electricalcharacterization Goal is “Electrical characterization of PV, software (TCAD) / hardware comparison & calibration” Task Leader: hans.tuinhout@nxp.com MODERN 2010 Review March 1st, 2011

  45. Partners:NXP, AMS, IMEP, UNET, LETI, NMX, STF2, ST-I, UNGL Progress: extension of Mismatch characterization to non Silicon technologies D2.3.2 (ST-I, NXP, due M18, see next slides): “Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices. Report on 1/f noise dispersion behavior in 45nm bulk CMOS” Nextactivities: D2.3.3 (STF2, NXP, UNET, AMS, LETI, due M30) « Identification of most relevant process variations in planar bulk CMOS devices down to 32nm, parameter fluctuation effects based on hardware Sources for PV in new device architectures, suitable for 22nm CMOS; major deltas in comparison to standard planar bulk CMOS” D2.3.4 (NMX, NXP, due M36) « Report on high-level models, both analytical and graphical , for PV of Non-Volatile-Memory devices. Report on 1/f noise dispersion behavior in 32 nm planar bulk CMOS” Task 2.3 Progress MODERN 2010 Review March 1st, 2011 45 45

  46. AlGaN 0.04um GaN 1um AlGaN 0.4um AlN 0.18um Si(111) 500um • WP2 D2.3.2 : Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (STI) Process variation impact on SIC diode (left) and AlGaN/GaN HEMT (right) Above HW data support TCAD validation in T2.1 MODERN 2010 Review March 1st, 2011

  47. WP2 D2.3.2 : 1/f noise dispersion characterization of 45 nm bulk CMOS (NXP) Id noise currentspectra (1Wafer, 65dies): Over 2 orders of magnitude Area Scaling of LF Noise dispersion preservedfrom 180nm to 45nm Comparable noise dispersions in 65nm/45nm LF noise Compact modelsfromearliernodesapply to 45nm MODERN 2010 Review March 1st, 2011

  48. T2.4: Correlation between PV and reliability, reliability modelling Goal: To develop and validate different level of models and tools for transistor level reliability that correlate reliability to PV and can be used at higher levels of the design process (AMS, IMEP, UNET, TUW, UNCA, UNGL) Task Leader: Jong-mun.park@austriamicrosystems.com  MODERN 2010 Review March 1st, 2011

  49. Partners:AMS, IMEP, UNET, TUW, UNCA, UNGL Activitydoneso far - D2.4.1 “Specification of considered degradation effects, modelling approaches and device parameters”. - NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations. - Initial physics-based analytical model for NBTI to implement in circuit simulator. - Time dependent modeling of degradation for NBTI & HC. Plan for D2.4.2 deliverable (M24): - TCAD reliability simulations focused on HV-CMOS. - Hot-Carrier lifetime model for HV-CMOS by modified Hu-model. - Threshold Voltage MismatchInduced by Hot-Carrier in 65 and 45 nm TechnologyNode. Plan for D2.4.3 deliverable (M33): - Statistical compact Models will be extracted at different levels of NBTI and PBTI. - Time dependence of the statistical compact models will be provided based on NBTI and PBTI models of trap charge as a function of time. - Analytical NBTI and HC model developments for LV- & HV-CMOS. Remains challenging task for HV-MOS devices, because of coupling between degradation effects and others (self-heating,…). WP2 Task 2.4 Progress MODERN 2010 Review March 1st, 2011 49 49 49

  50. WP2/ Task 2.4 contributions MODERN 2010 Review March 1st, 2011

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