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MIPS R2000 Architecture and Assembly (Part 1)

MIPS R2000 Architecture and Assembly (Part 1). CPU Registers Byte Order Addressing Modes CISC/RICS Comparisons. MIPS R2000 CPU and CFU. CPU Registers. MIPS CPU has 32 general purpose registers Each register can be referred to as $n , where n is the register number

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MIPS R2000 Architecture and Assembly (Part 1)

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  1. MIPS R2000 Architecture and Assembly(Part 1) CPU Registers Byte Order Addressing Modes CISC/RICS Comparisons

  2. MIPS R2000 CPU and CFU

  3. CPU Registers • MIPS CPU has 32 general purpose registers • Each register can be referred to as $n, where n is the register number • Within these 32 registers, the convention rules are: • Register 0 ($0) always contains zero • Register 1 ($1) is reserved for assembly • Register 2-7 are used for passing parameters in subroutine call • Register 8-15, and 24-25 are available for use. Values in these registers must be saved by caller if data need to be preserved across function call • Register 16-23 are available for use. Values in these registers must be saved by callee in order to preserve data across function call. • Register 26-27 are reserved for OS kernel • Register 28,29,30,31 are global area data pointer, stack pointer, frame pointer, and return address register, respectively.

  4. CPU Registers (cont.) • Co-processor 0 also contains registers for handling exception. These registers are named as: • BadVAddr: contains memory address at which exception occurred • Status: contains interrupt mask and enable bits • Cause: contains exception type and pending interrupt bits. • EPC: Address of instruction that caused exception • These special registers can be accessed by the lwc0, mfc0, mtc0, and swc0 instructions.

  5. CPU Registers (cont.) The Status Register The Cause Register

  6. Byte Order Processors can number the bytes with a word to make the byte with lowest number either the leftmost or the rightmost one. The convention used by a machine is its byte order. MIPS processors can operate with either big-endian or little-endian byte order Byte number Or

  7. Addressing Modes • MIPS is a load/store architecture: only load/store instructions can access memory • Computation must be done on registers • Here are addressing modes for load/store instructions

  8. RICS Load/Store architecture All instructions have equal length of 4 bytes Every register can be used in every instruction Delay branch CICS Not Load/Store arch. Instructions have variable lengths Not all registers can be used in all instructions (e.g. MUL instruction) There is no delay branch RICS/CICS Comparison

  9. RICS architecture is a load/store architecture All instructions have equal length of 4 bytes All registers can be used in any instructions Conventional rules for register usage are not enforced by the hardware, but to guarantee the correctness of the program if followed. Sections 2.1-2.3 of the printed lecture notes have been covered in today discussion Sections 2.4 and 2.5: your own reference resources SGI machines in CSIF have MIPS CPU Will cover Section 4 next time Closing Remarks

  10. int x; main() { x = 100; addone(&x); printf("%d\n",x); exit(1); } void addone(int * y) { *y = *y + 1; } Function Call Illustration: MIPS Version of AddOne.s

  11. .data x: .word .text .globl main main: li $2,100 la $4,x sw $2,x jal addone …… .text .globl addone addone: lw $2,0($4) addu $2,$2,1 sw $2,0($4) j $31 Function Call Illustration: MIPS Version of AddOne.s

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