C.A.D. Intellectual Agenda

1. C.A.D. Intellectual Agenda • Roadmapping: “Living Roadmap” to connect applications, architectures, components, technologies • Design envelopes; Impacts of innovations; FCRP portfolio gaps • Synergies: Drivers, Power-Energy, Reliability, C2S2 Fabrics, MSD, IFC • Focus on SiP physical implementation platforms (CLC, SOS) • Huge hole in FCRP understanding • Need technology and cost modeling, tools, implementation, roadmapping • Concrete high-end design driver (initially, CLC SiP driver highlighting logic-DRAM integration, DARPA MSP (Boeing STAP)) • Interfaces and standards (“infrastructure”) for design process • Internal to flows and methodologies • External: down (manufacturing variability models, mask flow handoff, cluster tool abstractions, … ) or up (IO cells, signaling standards, logic, system-level, …) • Measurement and quantification of design quality, design productivity

2. Concrete Outcomes • Task 1: Living Roadmap (from applications through ITRS technologies) • Cost-aware • Gaps  research + tool needs • Manufacturing handoff, die-package interface, variability, global signaling, synchronization, power delivery, robustness, … • GTX grows into a system-level analysis tool that is validated with design drivers • Task 2A: Develop SiP implementation platforms • Platform-specific tools and roadmapping • Task 2B: High-End (“Radar on a Chip”) Driver • Demonstration vehicle for overall GSRC methodology and CLC SiP-specific tools • Driver scaling + extrapolation • Integration paths for GSRC’s and other design methodologies • Task 3: Design process infrastructure • Design data models and interfaces  current enablers, future standards • Reusable, composable solvers  rapid flow synthesis/optimization • Concrete realizations of GSRC and other methodologies • with metrics and automated evaluators (bX)

3. Working Sessions • Goals • Drivers: Which ones? How they unify GSRC activities? Key research gaps? Roadmaps of functional requirements, technology showstoppers • Roadmapping: PED and Reliability • Design Infrastructure: OpenAccess data model and extensions; mini-flows and benchmarking (placement focus) • Today 10:30 – noon (joint with PED and Reliability) • CLC SIP and MSP, Radar-on-Chip Driver (Dai) • PicoRadio (PicoNode) Driver (Rabaey) • Today 1:00 – 2:30 pm • Home Gateway Driver (Kulkarni, Keutzer, Hwu) – brainstorming session • Today 3:00 – 4:00 pm • Roles of Drivers in new GSRC

4. Driver Discussions • Which ones? • How do they unify GSRC activities? • Key research gaps? • Roadmaps of functional requirements, technology showstoppers • Today 10:30 – noon (joint with PED and Reliability) • CLC SIP and MSP, Radar-on-Chip Driver (Dai) • PicoRadio (PicoNode) Driver (Rabaey) • MicroLab (alternative space) (Gupta) • Today 1:00 – 2:30 pm • Home Gateway Driver (Kulkarni, Keutzer, Hwu) – brainstorming session • Today 3:00 – 4:00 pm • Roles of Drivers in new GSRC

5. Driver Discussions • A DRIVER IS: • A concrete design for a specific application • (Lots of $, very few papers  ) • WHAT (D&T) PROBLEM IS THE DRIVER TRYING TO GET US TO SOLVE? • Continuation of the Moore’s Law for COST • Scalability of design or its infrastructure • Conceptualization (modeling, representation, validation) of systems • Unreliability and Unpredictability at component level • (Validation should be on this list, but how exactly are the drivers such as Radar-On-Chip driving validation?) • (Should Power be a first-class citizen?) • (N.B.: “Mixed-*” is mostly implicit in Conceptualization) • WHAT ARE DELIVERABLES ASSOCIATED WITH A DRIVER? • Design data (spec, arch, netlist, implementation, simulation, verification) and hardware • Tools

6. Driver Discussions • Axes for Drivers: • Metrics: heterogeneity, performance, power, size, reliability/RAS, cost • Impact: intrinsic value, interest (DARPA? HP/IBM/? Or Bechtel/PGE/?), technology leading edge • Synergy: semiconductor technologies, bridges within GSRC, package, system • System-Level vs. Fabric/Block Level • Application-level vs. implementation-level challenges • Bottom-up super-components (= top-down subsystems) that enable system: are these created by GSRC or C2S2? • Candidates • Batteryless • Ambient embedded networked sensing (= proxy for “next-gen”) • PicoNode, LabOnChip, MICA, SmartDust • High-performance computing • SIP / stacking: Radar On Chip: STAP DSP + Memory integration, CLC-SIP physical platform • General-purpose computing (500 5GHz MIPS cores on chip) • Utility computing (data center

7. Driver Discussions • Drivers + Infrastructure = third dimension • Are we picking drivers as a minimum-size cover, or are we picking drivers as “impactful”? Need to bound the goals, scope, … of this discussion • Communication-based, soft systems • DFX: Test, Verification, Power, Reliability, … • Other • Logistics • Leveraging (“how we do it now”), not building (rather, “hypothesis testing”) • Common access • Need a driver taxonomy + metrics: access/interfacing, heterogeneity, etc. • Links: OpenGIS.org, Security (SEC Disaster Recovery + Business Continuance), Recover-Oriented Computing, … • Home Gateway: How does drive VLSI and IC design? • What criticality is being overcome by spending $$$ on this driver?

8. PD Open Problems (Payman and Amir) • Incremental • Combined Placement and Floorplanning • <Clustering cells; Floorplanning clusters+blocks; Placing cells> locks solution into a bad subspace • Timing is a constraint (not an objective); WL is an objective • Problem = lack of understanding of interrelationships between different objectives, e.g., timing, area (fixed-die) and congestion • N.B.: WL may not really be an objective: it is a proxy for congestion (area) • Issue of capturing timing in top-down partitioning-based placement (partitioning is net-based; timing is path-based) • How is SI solved at placement? • IR drop placement? IR drop has impact on timing and reliability and hence important • Variability-aware placement?

9. PD Open Problems (Payman and Amir) • Thermal placement (not just dynamic power minimization) • Given activities of all gates, find a placement to minimize a linear combination of dynamic power and maximum thermal variation • Hierarchy? • Probably moving to • Datapath-based (timing-constrained) placement • People have tried but have not achieved notably better results • 2 literature from late 1980’s: Ebeling et al. subgraph isomorphism, Odawara/Szymanski/Nijssen-Jess/Varadarajan-Arikati on regularity extraction

10. PD Open Problems (Payman and Amir) • Power implications (voltage islands) • Chuck also mentions this • Clock gating • Multi-Vdd islands: granularity of several hundred cells (?) – 1-2 rows min in V, stripe pitch min in H • Ground islands (shutdown of blocks keeping memory partially powered up) • Cf. Amir’s work at Northwestern ~1995 • Placement for BIST (check with Tim Cheng et al.) • Signal Integrity Issues (crosstalk handling at floorplan and placement) • Clock distribution • Suggestion: Single-width, single-pitch cell layout, synthesis, place and route flow: WOULD BE HEROES !!! (PhasePhirst!, SCAAM, etc. == next-generation lithography proposals, all of which depend on “hyper-resolution” (“2-beam imaging”)  basically, only one direction and one pitch will print (the layout is a subset of a grating). Goal: C.A.D. people should prove a one-time, bounded hit on Moore’s Law (e.g., 30% density) but then scalability of SP&R thereafter. • X, Y Architectures March 5th EE Design ? • Design for Variability • Backend Process Optimization • Complex objective: marketing, methodology, integration • Marketing: BEOL should be optimized for many designs (derivatives, etc.) – range of size, frequency, etc. • Methodology: Crosstalk, IR drop, routing density, etc. • Statistical information : %WL per layer, %designs having X #gates, Y MHz, • Integration: cost of fabrication (e.g., AR limits, low metal-layer count, #layers, thickness (mfg throughput, pitch LBs from AR limits, …))

11. Working Sessions • Friday parallel session #1: Roadmapping • 9:00 – 11:00am (joint with PED and Reliability) • Background (Energy, Reliability, Variability) • Panel: PED Roadmapping Needs and Research Gaps • 11:00am – noon • Roadmapping of Process Variability, Cost Optimizations • Friday parallel session #2: Infrastructure, Benchmarking • 9:00 – 10:00am • BX and Benchmarking Status • 10:00am – 11:00am • Placement-Centered Directions (Mini-Flows, New Problems) • 11:00am – noon • Concrete steps with OpenAccess • Friday 1:30 – 2:30pm • Discussion of C.A.D. Roles in the “New GSRC”: collaborations, projects, milestones