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MonolithIC 3D ICs

MonolithIC 3D ICs. HKMG – Gate Last - Flow. MonolithIC 3D Inc. , Patents Pending. Figure 3 Using ion-cutting to place a thin layer of monocrystalline silicon above a processed (transistors and metallization) base wafer . Cleave using <400 o C anneal or sideways mechanical force. CMP.

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MonolithIC 3D ICs

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  1. MonolithIC 3D ICs HKMG – Gate Last - Flow MonolithIC 3D Inc. , Patents Pending MonolithIC 3D Inc. , Patents Pending

  2. Figure 3Using ion-cutting to place a thin layer of monocrystalline silicon above a processed (transistors and metallization) base wafer Cleave using <400oC anneal or sideways mechanical force. CMP. Hydrogen implant of top layer Flip top layer and bond to bottom layer Oxide p- Si Top layer Oxide p- Si H p- Si H p- Si Oxide Oxide Oxide Oxide Oxide Bottom layer Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today MonolithIC 3D Inc. , Patents Pending

  3. Monolithic 3D ICs Using SmartCut technology - the ion cutting process that Soitec uses to make SOI wafers for AMD and IBM (million of wafers had utilized the process over the last 20 years) - to stack up consecutive layers of active silicon (bond first and then cut). Soitec’s Smart Cut Patented* Flow(access link for video). *Soitec’s fundamental patent US 5,374,564 expired Sep. 15, 2012 MonolithIC 3D Inc. , Patents Pending

  4. Monolithic 3D ICs Ion cutting: the key idea is that if you implant a thin layer of H+ ions into a single crystal of silicon, the ions will weaken the bonds between the neighboring silicon atoms, creating a fracture plane (Figure 3). Judicious force will then precisely break the wafer at the plane of the H+ implant, allowing you to in effect peel off very thin layer. This technique is currently being used to produce the most advanced transistors (Fully Depleted SOI, UTBB transistors – Ultra Thin Body and BOX), forming monocrystalline silicon layers that are less than 10nm thick. MonolithIC 3D Inc. , Patents Pending

  5. Leveraging Gate Last + Innovative Alignment Gate Last was invented since Hafnium Oxide (HfO2) is sensitive to high temperature Transistors are first formed with “dummy gates” and “dummy oxide” using conventional high temperature process Than “dummy gates” and “dummy oxide” are etched away and replaced with Hafnium Oxide and High K Metal Gate (HKMG) In a monolithic 3D flow this two phase are broken to before layer transfer (“smart-cut”) and after Conventional process is first done on the donor wafers Than the top layer is transferred (“smart-cut”) onto a carrier and than annealed Than the top layer is transferred on target wafer Than the dummy gate and oxide are replaced to HfO2 and HKMG Than connection are made to the base wafer using “smart allignment” through the very thin single crystal layer (~50nm) 5 MonolithIC 3D Inc. Patents Pending

  6. Starting with Conventional Process Forming ‘Dummy” Gate and Oxide on Donor Wafer NMOS PMOS Poly Oxide Donor wafer • Fully constructed transistors attached to each other; no blanket films. • proprietary methods align top layer atop bottom layer Device wafer 6 MonolithIC 3D Inc. Patents Pending

  7. A Gate-Last Process for Cleave and Layer Transfer Poly Step 1 (std): On donor wafer, fabricate standard dummy gates with oxide, poly-Si Oxide S/D Implant ILD • Step 2 (std): Std Gate-Last • Self-aligned S/D implants • Self-aligned SiGe S/D • High-temp anneal • Salicide/contact etch stop or faceted S/D • Deposit and polish ILD CMP to top of dummy gates 7

  8. A Gate-Last Process for Cleave and Layer Transfer Step 3. Implant H for cleaving H+ Implant Cleave Line • Step 4. • Bond to temporary carrier wafer • (adhesive or oxide-to-oxide) • Cleave along cut line • CMP to STI Carrier STI CMP to STI 8 MonolithIC 3D Inc. Patents Pending

  9. A Gate-Last Process for Cleave and Layer Transfer Carrier • Step 5. • Low-temp oxide deposition • Bond to bottom layer • Remove carrier Oxide-oxide bond Remove (etch) dummy gates, replace with HfO2 and HKMG • Step 6. On transferred layer: • Etch dummy gates • Deposit gate dielectric and electrode • CMP • Etch tier-to-tier vias thru STI • Fabricate BEOL interconnect 9 MonolithIC 3D Inc. Patents Pending

  10. Novel Alignment Scheme using Repeating Layouts Oxide Landing pad Through-layer connection Bottom layer layout Top layer layout 10 MonolithIC 3D Inc. Patents Pending Even if misalignment occurs during bonding  repeating layouts allow correct connections. Above representation simplistic (high area penalty).

  11. Smart Alignment Scheme Oxide Landing pad Through-layer connection Bottom layer layout Top layer layout 11 MonolithIC 3D Inc. Patents Pending

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