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Review

Review. Coupled model definition. Generator. out. Queue. throughput. cpuusage. in. arrived. out. done. solved. Transducer. in. out. CPU. Coupled Model specification in CD++. [top] components : trans@Transducer components : gen@Generator components : Consum Out : out

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Review

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  1. Review

  2. Coupled model definition Generator out Queue throughput cpuusage in arrived out done solved Transducer in out CPU

  3. Coupled Model specification in CD++ [top] components : trans@Transducer components : gen@Generator components : Consum Out : out Link : out@gen arrived@trans Link : out@gen in@Consum Link : out@Consum solved@trans Link : out@trans out [Consum] components : qu@Queue components : proc@Processor in : in out : out Link : out@qu in@proc Link : out@proc done@qu Link : out@proc out Link : in in@qu out top Consum gen in out in in out out arrived qu trans proc done stop solved out out

  4. Modeling State-Based DEVS Models in CD++

  5. Examples of Application - DEVS • Alpha-1: a simulated computer with educational purposes. Basic components built as DEVS models. • Models of an Intel 8086 CPU and DSP processors. • Models of computer communication/networking: basic routing algorithms. • Plant models: autonomous robots together with classification/conveyor belt system. • ATLAS: a specification language for urban traffic models (high level specifications mapped in Cell-DEVS)

  6. A complex example: Alfa-1 computer • Theoretical studies about Computer Architecture and Organization. • Analysis of existing architectures; little emphasis into designing new ones. • Components studied individually: interaction? • No practical skills for the students. • Multiple organization levels: inter-level relationship? • Experimental evaluation and proposal of improvements. PROPOSAL  CONSTRUCTION OF A SIMULATED COMPUTER TO SOLVE THESE PROBLEMS. SIMULATION WITH EDUCATIONAL PURPOSES. DEVS FORMALISM: improved definition of the models

  7. Processor Architecture

  8. Processor architecture • “Flat” memory. Base and Size registers. • 520 integer registers: Eight global, and the remaining divided in windows of 24 registers: input, output and local registers for each procedure. • 5-bit register, CWP (Circular Window Pointer). • 32-bit WIM register (Window Invalid Mask, one bit per window) avoids the superposition with a window in use by another procedure. • Several internal registers. Two program counters.

  9. Architecture implementation (DEVS models) INC/DEC = < X, S, Y, int, ext, , D >. • XÎ {1,...,32}  {0,1} ; • S Î { OP }  { FCOD }  { RES } ; • Y Î {0,1} ; Model &IncDec::externalFunction( const ExternalMessage &msg ) { if( _FCOD == 1 ) increment; else decrement; this->holdIn(active, preparationTime); return *this; }

  10. Architecture implementation (DEVS models) Model &IncDec::internalFunction( const InternalMessage & ) { this->passivate(); return *this ; } Model &IncDec::outputFunction(const InternalMessage &msg){ for (int i=0; i<5; i++) { // If OP0..4 is different of last output if (_RES[i]!=_OLD[i]) { // send OP0..4 sendOutput(msg.time(),RESj, _RES[j]); _OLD[j]=_RES[j]; } } return *this ; }

  11. Coupled model: Address Unit CM = < X, Y, D, {Mi}, {Ii}, {Zij}, select > X= {OPAn, OPBn / OPAn, OPBn Î {0,1} }; • Y = {EQ, LW / EQ, LW Î {0,1} }; • D = {NOT_n_1, NOT_n_2, XOR_n, AND_n_1, AND_n_2 }; where each is an atomic defining the corresponding building block; I NOT_n_1= { AND_n_1 }; I XOR_n= {NOT_n_2 }; I NOT_n_2= { Self }; I AND_n_2= { Self }; I AND_n_1= { AND_n2 }; I self= { Self, NOT_n_1, AND_n_1, XOR_n}; Zij is built using I ; and select = D .

  12. set 0x12345678, %r1 ! Load register 1 with 0x12345678 st %r1, [dest] ! Store it in the "dest" variable sth %r1, [dest+4] ! Store the high half-word sth %r1, [dest+10] stb %r1, [dest+12] ! Store the last byte stb %r1, [dest+17] stb %r1, [dest+22] stb %r1, [dest+27] unimp dest: .ascii " "

  13. Initial image • Addr. Memory Image Interpretation • ... • 040 11000010 00100000 00100000 01001000 Store reg 1 in addr 72 • 044 11000010 00110000 00100000 01001100 St high part of r1 in 76 • 048 11000010 00110000 00100000 01010010 St high part of r1 in 82 • 052 11000010 00101000 00100000 01010100 St high byte of r1 in 84 • 056 11000010 00101000 00100000 01011001 St high byte of r1 in 89 • 060 11000010 00101000 00100000 01011110 St high byte of r1 in 94 • 064 11000010 00101000 00100000 01100011 St high byte of r1 in 99 • 068 00000000 00000000 00000000 00000000 unimp • 072 00100000 00100000 00100000 00100000 "dest" var. (20: space) • 076 00100000 00100000 00100000 00100000 • ... • Final image • ... • 072 00010010 00110100 01010110 01111000 12 34 56 78 • 076 01010110 01111000 00100000 00100000 56 78 20 20 (20 = space) • 080 00100000 00100000 01010110 01111000 20 20 56 78 • 084 01111000 00100000 00100000 00100000 78 20 20 20 • 088 00100000 01111000 00100000 00100000 20 78 20 20 • 092 00100000 00100000 01111000 00100000 20 20 78 20 • 096 00100000 00100000 00100000 01111000 20 20 20 78

  14. Message */00:00:00:000/Root(00) to top(01) • Message */00:00:00:000/top(01) to CPU(05) • Message */00:00:00:000/cpu(05) to npc(10) • // Take the nPC • Message Y/00:00:00:000/npc(10)/out2/1.000 to CPU(05) • Message Y/00:00:00:000/npc(10)/out5/1.000 to CPU(05) • Message D/00:00:00:000/npc(10)/... to CPU(05) • // Send to pc-inc to increment the value • Message X/00:00:00:000/cpu(05)/in2/1.000 to pc_latch(11) • Message X/00:00:00:000/cpu(05)/op2/1.000 to pc_inc(13) • Message X/00:00:00:000/cpu(05)/in5/1.000 to pc_latch(11) • Message X/00:00:00:000/cpu(05)/op5/1.000 to pc_inc(13) • // Schedule activation of pc-inc model • Message D/00:00:00:000/pc_latch(11)/00:00:10:000 to CPU(05) • Message D/00:00:00:000/pc_inc(13)/00:00:10:000 to CPU(05) • Message D/00:00:00:000/pc_latch(11)/00:00:10:000 to CPU(05) • ...

  15. Message */00:00:00:000/top(01) to CPU(05) • // Arrival to the CU and activation of the components • Message */00:00:00:000/cpu(05) to cu(43) • Message Y/00:00:00:000/cu(43)/a_mux_reg/1.000 to CPU(05) • Message Y/00:00:00:000/cu(43)/b_mux_reg/1.000 to CPU(05) • Message Y/00:00:00:000/cu(43)/enable_alu/1.000 to CPU(05) • Message Y/00:00:00:000/cu(43)/addr_mux/1.000 to CPU(05) • Message Y/00:00:00:000/cu(43)/ir_latch_en/1.000 to CPU(05) • ... • Message */00:00:10:000/cpu(05) to pc_latch(11) • Message D/00:00:10:000/pc_latch(11)/... to CPU(05) • // Update the nPC • Message */00:00:10:000/cpu(05) to pc_inc(13) • Message Y/00:00:10:000/pc_inc(13)/res3/1.000 to CPU(05) • Message Y/00:00:10:000/pc_inc(13)/res5/1.000 to CPU(05) • Message D/00:00:10:000/pc_inc(13)/... to CPU(05) • ... • //Memory returns the first inst. • Message */00:00:20:001/top(01) to mem(02) • Message Y/00:00:20:001/mem(02)/dtack/ 1.000 to top(01) • Message Y/00:00:20:001/mem(02)/out_data2/ 1.000 to top(01) • Message Y/00:00:20:001/mem(02)/out_data3/ 1.000 to top(01)

  16. Message X/00:00:20:001/top(01)/in_dtack/ 1.000 to bus(03) • Message X/00:00:20:001/top(01)/in_data2/ 1.000 to CPU(05) • Message X/00:00:20:001/top(01)/in_data3/ 1.000 to CPU(05) • Message X/00:00:20:001/top(01)/in_data6/ 1.000 to CPU(05) • Message X/00:00:20:001/top(01)/in_data13/ 1.000 to CPU(05) • Message X/00:00:20:001/top(01)/in_data14/ 1.000 to CPU(05) • Message X/00:00:20:001/top(01)/in_data20/ 1.000 to CPU(05) • ... • Message X/00:00:20:001/top(01)/in_data31/ 1.000 to CPU(05) • Message D/00:00:20:001/bus(03)/00:00:00:001 to top(01)...

  17. DEVS Real-Time simulator event_time associated in_port out_port value deadline 00:05:000 00:05:600 in01 out01 1 00:09:000 00:09:400 in02 out02 2 00:15:500 00:16:200 in03 out03 3 00:19:000 00:19:700 in04 out04 4 Output associated result out_port value time deadline 00:05:500 00:05:600 succeeded out01 1 00:09:300 00:09:400 succeeded out02 2 00:17:100 00:16:200 not succ. out03 3 00:19:900 00:19:700 not succ. out04 4

  18. Alarm clock

  19. Vending Machine

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